I am attaching my circuit here. With Cload >= 1nF, circuit is very slow to simulate, sometimes it will do the job, other times it gets stuck in pseudo transient analysis.
Any help or direction will be appreciated.
This circuit works well with Simetrix.
The schematic you provided is corrupted or encrypted. Try to export circuit.qsch or circuit.cir
Change the extension to zip.
Replaced Ã-Device with VCCS_Limit1 which created based on your description in this post. Now can run this simulation in about 1 seconds.
VCCS with limter? - QSPICE - Qorvo Tech Forum
There is a fundamental different of the VCCS in your previous post and MULTGMAMP Ã-Device. MULTGMAMP Ã-Device Iout return through VDD/VSS instead of GND (0 node). This can introduce a fundamental different in the circuit when you replace Simetrix VCCS with a MULTGMAMP Ã-Device.
In addition, you added 4 text description in schematic but forgot to comment them, where simulation won’t run after unzip your circuit.
1. 2 stage simple amp model with slew rate 2V/uS and
2. Voltage Feedback Network for constant voltage at DUT
3. DUT Load
4. Gain = 3
Remove .txt to unzip modified schematic
Final_Model in 2.rar.txt (6.8 KB)
Thanks for providing updated and corrected schematics. problem now is when Cload is 100nF , simulation throws fatal error.
Add gshunt=1e-9 and maxstep=100n can simulate this circuit with Cload at 1nF or 100nF
I don’t know what model of op amp, but I suspect it won’t like having excessive voltage applied to its input. This doesn’t mean it occurs in steady state, but it could be when calculating the operating point in one of the iterations. I suggest putting an output voltage limiter on subcircuit X7.
An alternative approach is to do a .Tran 1m uic analysis. The count time should ensure that the circuit is established. Measure the point voltages, then set them with .nodeset and then .IC.
A good tool is available in LTspice - Savebias and Loadbias.
Do you mean I need to limit the output voltage of Gain 3x OPA593?
Maybe I should limit the output voltage of VCCS_Limit block?
This model is from TI.
I will try with uic and see what happens
Can you please help here? What is the issue with Qspice for these kind of models from TI?
I’ve had similar issues with just about every TI op amp model i have been using in my circuits as well. Small changes in resistor and or capacitor values cause fatal errors that otherwise don’t occur in LT Spice.
Did you attempt the recommended running the .Tran 1m uic analysis as recommended? This results in appropriate graphing, but inaccurate values shown at live probe points on circuit for me… But it has worked so far…
As mentioned by @Still_Learing, we discussed about TI opamp in this post and the best solution so far is to skip .op by adding UIC in .tran directive. My impression is that, the major reason simulator got stuck in calculating dc operating point, which is performed before .tran. Here is the post for reference
Source Stepping Failed - OPA2991 Sim - QSPICE - Qorvo Tech Forum
If you take a look of TI opamp sub-circuit, you can observe it uses a lot of tables and switches, possibly that is what the challenge come from.
As a user, I don’t have much can do. Please consider to email your circuit to Mike to see if any further treatment in Qspice can handle TI opamp pspice model. You can find his contact in Qspice : HELP > About Qspice
By the way, as mentioned last time, by adding .options for gshunt and MAXSTEP, I can simulate your circuit at 1nF or 100nF without the need of using UIC. Is there a condition fail this simulation again?
it worked… But with MAXSTEP = 100n, sim takes too much time
trtol by default 1 like LTspice?
LTspice - Trtol=1
Qspice - Trtol=2.5
Other spice simulators Trtol=7