Has anyone had any success getting the LM5156x model running in QSPICE? It seems like there are several incompatibilities, and I’ve tried modifying the model appropriately, but it still doesn’t run in QSPICE, The unencrypted PSPICE model is here.
Refer to this post and upload your Qspice schematic that is built following the demo circuit provided by TI.
General Guide to Import a TI SPICE Model - QSPICE - Qorvo Tech Forum
Thanks, Kelvin, sure. Attached is my circuit. It’s identical to the TI PSPICE boost demo circuit with the following exceptions:
- I didn’t add caps in parallel with the voltage source. Didn’t see the point for purposes of getting the model to run.
- I used a different diode and FET from the models used in PSPICE.
- I didn’t add a 10 ohm resistor at the top of the feedback divider, since I’m not doing a loop gain measurement.
The model file is attached as well. I changed ^ to ^^ in 2 places.
The original model file is here, for reference: LM51561 data sheet, product information and support | TI.com
The simulation fails with:
Warning: Using skipbp
Fatal error: Timestep too small(1.25e-19) at t=0
max timestep is set to 20n as in the PSPICE simulation.
LM5156 test circuit.qsch (20.2 KB)
LM5156-Q1_TRANS.LIB (29.1 KB)
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It seems Qspice cannot obtain a DC solution from this subcircuit. The same netlist can run in LTspice but not in Qspice. Changing ^ to ^^ in this model is not essential, as those .subckt are just there but not called by the LM5156. The real challenge is in the model and not external component, as both Pspice and LTspice can run this model but Qspice stopped at t=0s.
I had to mask multiple devices in this subcircuit netlist to get this model to run, so what is causing difficulty for Qspice may not be easy to identify. Let’s see if anyone in the forum can provide additional assistance.
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Thanks again, Kelvin, really appreciate your time and effort in supporting this forum and QSPICE users!
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Possibly I figure a way for the model to work in Qspice. Will share more information after I further modify this library with logic devices from Pspice E-source syntax to Qspice ¥-device. I have to make sure replacement logic subcircuit is fully equivalent.
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Here is the replication of two examples from the TI LM5156 Pspice library: ‘Startup’ and ‘Steady_State’, with a modified library. I recommend using the behavioral switch and diode, as the Pspice version utilizes the behavioral switch, which can prevent the timestep from becoming too small. Setting the Maxstep in .tran is essential (20ns), this value is according to Pspice example.
LM5156-snvmbv9h-Startup.qsch (17.9 KB)
LM5156-snvmbv9h-Steady_State.qsch (17.9 KB)
LM5156-Q1_TRANS-Cleanup-Pspice.txt (26.0 KB)
LM5156-Q1_TRANS-Cleanup-Qspice.txt (25.9 KB)
Let me describe what I did. I have attached two library files: one is the original Pspice library, and the other is the modified Qspice library. TI uses the E-source if(,) function to implement logic devices, which is not optimized for Qspice. The Qspice timestep scheme is more dynamic than Pspice and LTspice, giving an advantage in simulation speed while maintaining high accuracy in state changes. But this poses a challenge for legacy logic implementations (in a very complex model likes TI model).
Qspice uses the ¥-Device as logic device. Therefore, my work involved modifying those TI Pspice syntax logic subcircuits from using E-source to Qspice ¥-Device. You can use Notepad++ and install the Compare plugin to compare the two .txt libraries and get a full list of what I changed. Here is an example of how I modified the AND2_BASIC_GEN subcircuit.
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Ґ1 LH LL Y RSRC=1 CAPVSS=1n
V1 LH 0 VDD
V2 LL 0 VSS
*RINT YINT Y 1
*CINT Y 0 1
LM5156-Q1_TRANS-Cleanup-Qspice_AB.txt (26.1 KB)
n
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I maintained external RINT and CINT is easier to track in the format, but I didn’t realize that moving these parameters into the ¥-Device could provide a speed boost.
I also noticed that you added Cjo to the diode model. It’s always great to learn from a master!
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Wow, thanks very much Kelvin and Bordodynov. Really appreciate the knowledge and support!
It was easier to change the logic gates by replacing the controlled sources E with B and adding the parameters Rser, Cpar!
For example:
.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
BE_ABMGATE1 YINT2 0 V=IF((V(A) > VTHRESH) ,VDD,VSS) Rser=1 Cpar={DELAY*1.3}
BE_ABMGATE2 Y 0 V=IF((V(YINT2) > VTHRESH) , VDD,VSS) Rser=1 Cpar=1n
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
BE_ABMGATE Y 0 V=IF((V(A) > VTHRESH) , VDD,VSS) Rser=1 Cpar=1n
.ENDS BUF_BASIC_GEN
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
bE_ABM Y 0 V=IF((V(INP) > V(INM)),VDD,VSS) Rser=1 Cpar=1n
.ENDS COMP_BASIC_GEN
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The calculation is accelerated due to the fact that the nodes of the circuit are thrown away, i.e. the matrix of the circuit reduces the order. The second important factor is that bad circuit nodes with steep edges are thrown out.
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