* Generated with LTspice2Qspice_Netlist.m (by KSKelvin)
* ANSI Encoding
*
*$
* LM5156-Q1
*****************************************************************************
* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
** Released by: Texas Instruments Inc.
* Part: LM5156-Q1
* Date: 09DEC2019
* Model Type: TRANSIENT
* Simulator: PSPICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: NA
* EVM Users Guide: NA
* Datasheet: SNVSBI7 –JULY 2019
* Topologies Supported: Boost, Flyback, SEPIC
*
* Model Version: Final 1.00
*
*****************************************************************************
*
* Updates:
*
* Final 1.00
* Release to Web.
*
*****************************************************************************
*
* Model Usage Notes:
* 1. The following features have been modeled
* a. UVLO and SYNC functionality.
* b. OVP,UVP and PGOOD.
* c. Over current Protection and Hiccup mode for LM51561.
* Keep Parameter LM51561=1 to enable Hiccup feature.
* d. Maximum duty cycle.
* 2. Model is validated across EVM corners for Start-up,Line and Load transient cases.
* 3. Temperature effects are not modeled.
* 4. Model is not validated for inverting configurations.
* 5. Frequency dithering functionality is not modelled.
*
*****************************************************************************
.SUBCKT LM5156-Q1_TRANS BIAS COMP CS DITHOFF FB GATE GND PGOOD RT SS UVLO_SYNC VCC PARAMS: SS=0 FAST_HICCUP=1 LM51561=0
C_U1_C7 VREF_INT FB 1f
R_U1_R1 0 COMP 5Meg
D_U1_D1 COMP U1_N16756926 D_D1
V_U1_V1 U1_N16756762 0 1.1
D_U1_D2 U1_N16756762 COMP D_D1
V_U1_V2 U1_N16756926 0 2.5
R_U1_R3 VREF_INT FB 100Meg
C_U1_C6 0 COMP 2p
X_U1_U3 VREF_INT FB 0 COMP VCCS_LIMIT PARAMS: IMIN=-200u IMAX=200u GAIN=2m
X_U2_U6 U2_N16760639 U2_N16760475 U2_N16761124 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U5 ENABLE_PWM_N HICCUP_START U2_N16760639 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U2_V_mask_steady U2_N16760475 0 PULSE 0 1 1.1u 1p 1p
V_U2_V3 U2_N16731322 0 2
X_U2_U1 U2_N16761124 ENABLE_PWM SS U2_N16731322 VREF_INT 0 SOFTST_GEN PARAMS: SS_TIME=1M ISS=10u VREF_VAL=1 SS=1 RDIS=1m
X_U7_U16 OVP U7_N16780463 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U7_V9 VCC1 U7_VCC_UVLO 0Vdc
X_U7_U17 U7_N16778942 U7_N16780463 ENABLE_PWM AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U7_U5 N02700 U7_N01325 BIAS_OK RISING_FALLING_EDGE_DELAY PARAMS: RISING_EDGE_DELAY=65u FALLING_EDGE_DELAY=0
E_U7_ABM4 U7_N16774788 0 VALUE { if( V(SYNCEXT)>0.5,1,V(ENABLE_OSC)) }
X_U7_U19 UVLO_SYNC U7_N01197 U7_N01325 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U7_U12 U7_VCC_OK OTP_DONE U7_N16774788 U7_N16778942 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U7_U1 U7_VCC_UVLO U7_N00374 U7_N00370 U7_N00412 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U7_U10 U7_N10154 U7_N11175 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U7_C1 U7_N16821281 0 1n TC=0,0
X_U7_U18 U7_N09742 BIAS_OK U7_N16829822 U7_N10154 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U7_I2 U7_N16812073 U7_N16818074 DC 1u
V_U7_V1 U7_N00370 0 0.063
D_U7_D4 U7_N16818074 U7_N16812073 D_D1
E_U7_ABM3 U7_N16818074 0 VALUE { LIMIT(V(U7_N16821281),0,6.85) }
X_U7_F1 U7_N16812081 VCC1 BIAS 0 VCC_GEN_UVLO_U7_F1
I_U7_I1 U7_N16812073 U7_N16812081 DC 35m
V_U7_V2 U7_N00374 0 2.85
D_U7_D6 U7_N16812081 U7_N16812073 D_D1
V_U7_V6 U7_0V 0 0
X_U7_U13 ENABLE_PWM ENABLE_PWM_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U7_U8 U7_N10154 U7_N10443 one_shot PARAMS: T=6500
V_U7_V8 U7_N16829822 0 PULSE 0 1 1u 1p 1p
X_U7_U3 U7_N00412 OTP_DONE BIAS_OK U7_VCC_OK AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U7_ABM2 U7_N16821141 0 VALUE { if(V(BIAS_OK)>0.5,V(BIAS),0) }
R_U7_R3 U7_N16821141 U7_N16821281 10 TC=0,0
V_U7_V3 U7_N01197 0 550m
X_U7_U11 OTP_DONE N12429 U7_N10443 U7_1V U7_N11175 U7_0V dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U7_V7 U7_1V 0 1
E_U7_ABM1 U7_N09742 0 VALUE { if(V(BIAS)>2.5,1,0) }
X_U3_U4 U3_N16756766 0 0 U3_SLOPE_RAMP VCCS_LIMIT PARAMS: IMIN=0 IMAX=100u GAIN=44m
X_U3_U5 PWM U3_N16762943 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U3_U2 U3_5V 0 0 N00537 VCCS_LIMIT PARAMS: IMIN=0 IMAX=1 GAIN=8.5u
X_U3_U1 U3_SLOPE_RAMP 0 0 CS VCCS_LIMIT PARAMS: IMIN=0 IMAX=100u GAIN=30U
X_U3_S1 CLK 0 U3_N16754008 0 GM_IPHASE_U3_S1
X_U3_S2 U3_N16763020 0 U3_SLOPE_RAMP 0 GM_IPHASE_U3_S2
E_U3_E2 U3_CS_BUF 0 CL 0 1
R_U3_R3 U3_N16754008 CL 20k
R_U3_R1 U3_CS_BUF N00537 4k
X_U3_U7 U3_N16762943 CLK ENABLE_PWM_N U3_N16763020 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U3_E1 U3_N16753444 0 CS 0 1
C_U3_C1 CL 0 1p
E_U3_ABM1 U3_N16756766 0 VALUE { if( V(PWM)>0.5,V(IRT),0) }
X_U3_U3 U3_SLOPE_RAMP 0 0 N00537 VCCS_LIMIT PARAMS: IMIN=0 IMAX=100u GAIN=10u
V_U3_V1 U3_5V 0 5
R_U3_R2 CL U3_N16753444 20k
C_U3_C2 0 U3_SLOPE_RAMP 1p TC=0,0
X_U4_S1 U4_N16795829 0 U4_N16792836 0 OSCILLATOR_SYNC_U4_S1
E_U4_ABM5 U4_TIME_PERIOD 0 VALUE { { {1/{V(U4_FREQ)}-(CLK_WIDTH+5n)} } }
E_U4_ABM6 U4_CURRENT 0 VALUE { IF(V(DMAX_PWM)>0.5,{ {Cosc*Vosc/V(U4_TIME_PERIOD)} },0) }
G_U4_ABM2I2 0 U4_N16792836 VALUE { V(U4_CURRENT) }
V_U4_V2 U4_N16797664 0 4
E_U4_ABM1 U4_FREQ 0 VALUE { 1+((V(U4_N16709079)*4.42e10)/(1+2*955*V(U4_N16709079))) }
E_U4_E1 U4_N16708731 0 ENABLE_OSC 0 0.5
X_U4_U3 ENABLE_OSC U4_ENABLE_OSC_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U4_C1 U4_N16792836 0 {Cosc} IC=0 TC=0,0
E_U4_ABM3 U4_N16709079 0 VALUE { if(V(SYNCEXT)>0.5,V(IRT)/2 ,V(IRT)) }
E_U4_ABM8 U4_DMAX_VTH 0 VALUE { V(U4_TONMAX)*{ {Cosc*Vosc/V(U4_TIME_PERIOD)} }/{Cosc} }
X_U4_U5 U4_N16792836 U4_DMAX_VTH U4_N16795644 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
D_U4_D1 U4_N16792836 U4_N16797664 D_D1
X_U4_U13 DMAX_PWM N16802185 U4_N16795644 CLK SRLATCHNOP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
C_U4_C10 0 U4_DMAX_VAL 1n TC=0,0
X_U4_H1 U4_N16708731 RT IRT 0 OSCILLATOR_SYNC_U4_H1
E_U4_ABM7 U4_TONMAX 0 VALUE { LIMIT((V(U4_DMAX_VAL)/V(U4_FREQ)),0,10m) }
E_U4_ABM4 CLK 0 VALUE { if(V(SYNCEXT)>0.5,V(SYNC_PULSE),V(CLK_INT)) }
R_U4_R7 U4_N16809972 U4_DMAX_VAL 10 TC=0,0
X_U4_U7 U4_N16795554 U4_N16795829 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
E_U4_E16 U4_N16809972 0 TABLE { V(U4_FREQ, 0) } ( (0,0.935)(.25e6,0.931)(.5e6,0.928)(.75e6,0.926)(1e6,0.923)(1.25e6,0.918)(1.5e6,0.906)(1.75e6,0.892)(2e6,0.878)(2.25e6,0.864) )
X_U4_U2 CLK_INT U4_FREQ RAMP U4_ENABLE_OSC_B oscillator PARAMS: CLK_WIDTH={CLK_WIDTH} VOSC={Vosc} COSC={Cosc}
X_U4_U6 U4_N16795644 U4_N16795554 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
X_U5_U9 U5_PWMEN N16716524 ENABLE_PWM_N ENABLE_PWM SRLATCHRHP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
R_U5_R2 0 U5_COMP_BUF_DIVIDED 50k
X_U5_U15 U5_N16714560 DMAX_PWM U5_PWMEN_DELAYED PWM AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U5_E1 U5_N00138 0 COMP 0 1
X_U5_U4 CUR_LIMIT FBCOMP U5_N16720791 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U14 U5_PWMEN U5_PWMEN_DELAYED BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=100n
X_U5_U6 U5_N16713533 U5_N16713639 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U11 U5_N16720791 U5_PWMEN U5_N16721037 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U1 N00537 U5_COMP_BUF_DIVIDED FBCOMP COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U5_U7 U5_N16713533 U5_N16714264 one_shot PARAMS: T=50
X_U5_U8 U5_N16713639 U5_N16714264 U5_N16714560 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U10 U5_PWM_INT U5_N16716985 U5_PWMEN U5_N16713533 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U5_ABM4 U5_N16716985 0 VALUE { if( V(SYNCEXT)>0.5,1,V(ENABLE_OSC)) }
X_U5_U2 CL U5_N16711915 CUR_LIMIT COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U5_R1 U5_COMP_BUF_DIVIDED U5_N00138 300k
X_U5_U13 U5_PWM_INT N00762 CLK U5_N16721037 SRLATCHNOP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
V_U5_V1 U5_N16711915 0 0.1
X_U10_U14 CLK_INT DISABLE_OSC U10_N16731610 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U10_U4 OTP_DONE U10_N00393 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U10_U16 U10_UVLO_B U10_N16736825 SYNC_PULSE AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U10_U13 CLK U10_CLK_DEL BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
X_U10_U17 UVLO_SYNC U10_UVLO_B BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
X_U10_U3 U10_N00253 N00303 U10_N16731610 SYNC_PULSE SRLATCHRHP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
X_U10_U10 SYNCEXT N00371 U10_N00393 U10_N00253 SRLATCHNOP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
X_U10_U18 UVLO_SYNC U10_N16736825 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
G_U8_ABMII1 U8_N16764954 UVLO_SYNC VALUE { 5u*{V(U8_UVLO_OK)} }
X_U8_U11 U8_VCC_50U_DELAY U8_VCC_GRT_4P5V U8_N16771826 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U1 UVLO_SYNC U8_N00098 U8_N00086 U8_UVLO_OK COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U8_U12 U8_UVLO_OK BIAS_OK U8_N16771826 U8_N00819 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U8_V3 U8_N16764954 0 5
X_U8_U8 U8_UVLO_OK_N CLK_INT U8_N00423 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U8_V1 U8_N00086 0 0.05
V_U8_V4 U8_N16769114 0 2.85
X_U8_U9 VCC1 U8_N16769114 U8_N16769752 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U8_U5 U8_N00819 U8_UVLO_OK_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U8_V2 U8_N00098 0 1.5
R_U8_R3 U8_N16769752 U8_VCC_50U_DELAY 50 TC=0,0
C_U8_C1 U8_VCC_50U_DELAY 0 1.443u TC=0,0
X_U8_U7 ENABLE_OSC DISABLE_OSC INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U6 ENABLE_OSC N00921 U8_N00423 U8_N00819 SRLATCHRHP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
X_U8_U10 VCC1 U8_N16770694 U8_VCC_GRT_4P5V COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U8_V5 U8_N16770694 0 4.5
V_U11_V3 U11_N00469 0 50m
X_U11_U6 U11_UVP U11_N16764586 asymmetric_delay PARAMS: RISING_EDGE_DELAY=25u VTHRESH=0.5 FALLING_EDGE_DELAY=1u VDD=1 VSS=0
V_U11_V4 U11_N00507 0 0.95
X_U11_U1 U11_FB_INT U11_N00117 U11_N00050 U11_N00194 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U11_V1 U11_N00050 0 50m
X_U11_U4 U11_N00545 U11_UVP_N BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=1000n
X_U11_S1 U11_N01195 0 PGOOD 0 PGOOD_U11_S1
X_U11_U7 U11_UVP_N U11_N16764044 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U11_V2 U11_N00117 0 1.1
X_U11_U8 U11_N16764586 ENABLE_PWM_N U11_N01195 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U11_E2 U11_UVP 0 U11_N16764044 0 1
X_U11_U3 U11_FB_INT U11_N00507 U11_N00469 U11_N00545 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U11_E1 U11_FB_INT 0 FB 0 1
X_U11_U2 U11_N00194 OVP BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=1000n
V_U6_V4 U6_N12050 0 0.5
X_U6_S34 U6_PWMBAR_DEL 0 U6_N00439 0 DRIVER_U6_S34
R_U6_R2 U6_N12807 U6_N12761 1
D_U6_D1 0 U6_N00439 D_D1
I_U6_I2 U6_N25217 U6_N00439 DC 1.5
X_U6_U11 PWM U6_PWMBAR INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U6_C2 0 U6_N12761 {(1.414*{DEAD_TIME_DRVHLOW_To_DRVLHIGH}-1n)}
D_U6_D4 U6_N00439 U6_N25217 D_D1
X_U6_S35 U6_PWM_DEL 0 VCC1 U6_N00439 DRIVER_U6_S35
D_U6_D2 U6_N00439 VCC1 D_D1
X_U6_U12 U6_PWM_DEL U6_PWM_B_DEL INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U6_I1 U6_N25217 GATE DC 1.5
R_U6_R1 U6_N12086 U6_N12016 1
C_U6_C1 0 U6_N12016 {1.414*{DEAD_TIME_DRVLLOW_DRVHHIGH+1n}}
E_U6_E1 U6_N12086 0 PWM 0 1
D_U6_D3 GATE U6_N25217 D_D1
X_U6_U238 U6_PWMBAR U6_N12761 U6_PWMBAR_DEL AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U234 U6_N12016 U6_N12050 U6_PWM_DEL COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U6_E2 U6_N12807 0 U6_PWM_B_DEL 0 1
V_V1 VCC VCC1 0Vdc
X_U9_U7 CLK HICCUP_START U9_N01120 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U5_ABM59 U9_DIS_HICCUP 0 VALUE { if({LM51561}<0.5,1,if(V(SS)<1.2,1,0)) }
X_U9_U1 U9_N00148 N00186 N02060 0 U9_N00377 U9_N00179 COUNTER PARAMS: MIN_PW=10N COUNT_RST=8
X_U9_U10 HICCUP_START N02977 U9_HICCUP_RESET U9_N00916 SRLATCHNOP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
X_U9_U2 FBCOMP U9_N00132 U9_N00148 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U9_U5 CUR_LIMIT U9_HICCUP_RESET U9_N00377 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U9_U3 CUR_LIMIT U9_N00132 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U9_U12 U9_N03226 HICCUP_END BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
X_U9_U11 U9_N03226 N03763 HICCUP_END U9_N01355 SRLATCHNOP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
X_U9_U4 HICCUP_END 8PWM_OK U9_N01644 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U9_U13 U9_N01644 U9_DIS_HICCUP U9_HICCUP_RESET OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U9_U6 CUR_LIMIT N00893 N02668 0 U9_HICCUP_RESET U9_N00916 COUNTER PARAMS: MIN_PW=10N COUNT_RST=64
X_U9_U9 8PWM_OK N02027 CUR_LIMIT U9_N00179 SRLATCHNOP_BASIC_NEW PARAMS: IC=0 THRESH=0.5 VDD=1 VSS=0
X_U9_U8 U9_N01120 N01327 N01300 0 HICCUP_END U9_N01355 COUNTER PARAMS: MIN_PW=10N COUNT_RST={32768-31744*{FAST_HICCUP}}
.IC V(COMP )={SS*1.5}
.PARAM clk_width=22.5n dead_time_drvhlow_to_drvlhigh=5n dead_time_drvllow_drvhhigh=5n vosc=1 cosc=2.262n
.ENDS LM5156-Q1_TRANS
*
*$
.subckt VCC_GEN_UVLO_U7_F1 1 2 3 4
F_U7_F1 3 4 VF_U7_F1 1
VF_U7_F1 1 2 0V
.ends VCC_GEN_UVLO_U7_F1
*
*$
.subckt GM_IPHASE_U3_S1 1 2 3 4
S_U3_S1 3 4 1 2 _U3_S1
RS_U3_S1 1 2 1G
.MODEL _U3_S1 VSWITCH Roff=100e6 Ron=1m Voff=0.2 Von=0.8
.ends GM_IPHASE_U3_S1
*
*$
.subckt GM_IPHASE_U3_S2 1 2 3 4
S_U3_S2 3 4 1 2 _U3_S2
RS_U3_S2 1 2 1G
.MODEL _U3_S2 VSWITCH Roff=100e6 Ron=1m Voff=0.2 Von=0.8
.ends GM_IPHASE_U3_S2
*
*$
.subckt OSCILLATOR_SYNC_U4_S1 1 2 3 4
S_U4_S1 3 4 1 2 _U4_S1
RS_U4_S1 1 2 1G
.MODEL _U4_S1 VSWITCH Roff=100G Ron=100m Voff=0.25 Von=0.75
.ends OSCILLATOR_SYNC_U4_S1
*
*$
.subckt OSCILLATOR_SYNC_U4_H1 1 2 3 4
H_U4_H1 3 4 VH_U4_H1 1
VH_U4_H1 1 2 0V
.ends OSCILLATOR_SYNC_U4_H1
*
*$
.subckt PGOOD_U11_S1 1 2 3 4
S_U11_S1 3 4 1 2 _U11_S1
RS_U11_S1 1 2 1G
.MODEL _U11_S1 VSWITCH Roff=100e6 Ron=100 Voff=0.2 Von=0.8
.ends PGOOD_U11_S1
*
*$
.subckt DRIVER_U6_S34 1 2 3 4
S_U6_S34 3 4 1 2 _U6_S34
RS_U6_S34 1 2 1G
.MODEL _U6_S34 VSWITCH Roff=1e6 Ron=1.9m Voff=0.2 Von=0.8
.ends DRIVER_U6_S34
*
*$
.subckt DRIVER_U6_S35 1 2 3 4
S_U6_S35 3 4 1 2 _U6_S35
RS_U6_S35 1 2 1G
.MODEL _U6_S35 VSWITCH Roff=1e6 Ron=4.1m Voff=0.2 Von=0.8
.ends DRIVER_U6_S35
*
*$
.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=0.1 )
*$
.SUBCKT ONE_SHOT IN OUT PARAMS: T=100
¥1 LH 0 OUT ¥0 ¥ IN ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ monostable Ton=T*1e-9 Rout=1m
V1 LH 0 1
.ENDS ONE_SHOT
*
*$
.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 25n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.model d_d1 d is=1e-015 tt=1e-011 rs=0.05 n=0.01
.ENDS DFFSR_RHPBASIC_GEN
*
*$
.SUBCKT Oscillator CLK FREQ RAMP SDWN PARAMS: CLK_WIDTH=20N VOSC=1 COSC=10P
V_Vref VREF_OSC 0 {Vosc}
C_Cramp RAMP 0 {Cosc}
X_Sdisch DISCH 0 RAMP 0 Oscillator_Sdisch
E_ABM1 TIME_PERIOD 0 VALUE { {1/{V(FREQ)}-(CLK_WIDTH+5n)} }
X_U2 CLK N16698680 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY={CLK_WIDTH}
X_U131 RAMP VREF_OSC CLK COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
D_D11 RAMP N16699162 D_Dosc
V_V45 N16699162 0 {Vosc+4}
G_ABMI3 N16699162 RAMP VALUE { {Cosc*Vosc/V(Time_Period)} }
X_U134 SDWN N16698680 DISCH OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
.model D_Dosc d is=1e-015 tt=1e-011 rs=0.01 n=0.1
.IC V(RAMP)=0
.ENDS Oscillator
*
*$
.subckt Oscillator_Sdisch 1 2 3 4
S_Sdisch 3 4 1 2 _Sdisch
RS_Sdisch 1 2 1G
.MODEL _Sdisch VSWITCH Roff=100G Ron=100m Voff=0.2 Von=0.8
.ends Oscillator_Sdisch
*
*$
.SUBCKT ASYMMETRIC_DELAY INP OUT PARAMS: Rising_edge_Delay=1 VTHRESH=0.5 Falling_Edge_Delay=1 VDD=1 VSS=0
¥1 LH LL INP1 ¥ INP ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
¥2 LH LL YIN4 ¥ YIN3 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
¥3 LH LL YIN2 ¥ YIN1 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
R_RINT INP1 YIN1 1 TC=0,0
C_CINT 0 YIN1 {1.443*Rising_edge_Delay} TC=0,0
D_D10 YIN1 INP1 D_D1
R_R1 YIN4 OUT 1 TC=0,0
R_ROUT YIN2 YIN3 1 TC=0,0
C_COUT 0 YIN3 {1.443*Falling_Edge_Delay} TC=0,0
C_C1 0 OUT 1n TC=0,0
D_D11 YIN2 YIN3 D_D1
.model D_D1 D is=1e-015 tt=1e-011 rs=0.005 n=0.1
.ENDS ASYMMETRIC_DELAY
*
*$
.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS INV_BASIC_GEN
*
*$
.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
¥1 LH LL YINT1 ¥ A ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
V1 LH 0 VDD
V2 LL 0 VSS
¥2 LH LL ¥ YINT3 YINT2 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A B ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ AND REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*
*$
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A B C ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ AND REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND3_BASIC_GEN
*
*$
.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A B C D ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ AND REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND4_BASIC_GEN
*
*$
.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ AND REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND2_BASIC_GEN
*
*$
.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B C ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ AND REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND3_BASIC_GEN
*
*$
.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B C D ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ AND REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND4_BASIC_GEN
*
*$
.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR2_BASIC_GEN
*
*$
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B C ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR3_BASIC_GEN
*
*$
.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B C D ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR4_BASIC_GEN
*
*$
.SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B C D E ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR5_BASIC_GEN
*
*$
.SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL N01 ¥ A B C ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS
¥2 LH LL N02 ¥ D E F ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS
¥3 LH LL ¥ YINT N01 N02 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR6_BASIC_GEN
*
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A B ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR2_BASIC_GEN
*
*$
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A B C ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR3_BASIC_GEN
*
*$
.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A B C D ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR4_BASIC_GEN
*
*$
.SUBCKT XNOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL ¥ YINT A B ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ XOR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS XNOR2_BASIC_GEN
*
*$
.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A B ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ XOR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS XOR2_BASIC_GEN
*
*$
.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL YINT ¥ A ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*
*$
.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
¥1 LH LL YINT1 ¥ A ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
¥2 LH LL YINT3 ¥ YINT2 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ OR REF=VTHRESH-VSS Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS BUF_DELAY_BASIC_GEN
*
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
¥1 LH LL Yint ¥ INP INM LH ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ HMITT Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*
*$
.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5 T=10
EIN INP1 INM1 INP INM 1
EHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }
¥1 LH LL OUT ¥ INP1 INM2 LH ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ HMITT Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 10K
RINM2 INM2 0 10K
.ENDS COMPHYS2_BASIC_GEN
*
*$
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
EIN INP1 INM1 INP INM 1
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
¥1 LH LL OUT ¥ INP2 INM1 LH ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ HMITT Rout=1m
V1 LH 0 VDD
V2 LL 0 VSS
R1 OUT 1 1
C1 1 0 5n
RINP1 INP1 0 1K
.ENDS COMPHYS_BASIC_GEN
*
*$
.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(S) > {VTHRESH}, V(B),V(A))}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS MUX2_BASIC_GEN
*
*$
.SUBCKT VCCS_LIMIT IN1 IN2 OUTP OUTN PARAMS: IMIN=0 IMAX=1m GAIN=30u
G_U1_ABM2I4 OUTP OUTN VALUE { {LIMIT((V(IN1) - V(IN2))*{GAIN}, {IMIN}, {IMAX})} }
.ENDS VCCS_LIMIT
*
*$
.SUBCKT Softst_Gen DISABLE_SS EN_SS SS_INT VDD VREF VSS PARAMS: SS_TIME=1m Iss=1u VREF_VAL=1 SS=0 Rdis=3k
D_D62 SS_INT VDD D_Dsoftstart
G_ABMII1 VDD SS_INT VALUE { IF(V(EN_SS) > 0.5,Iss,0) }
X_S1 DISABLE_SS VSS SS_INT VSS Softst_Gen_S1 PARAMS: Rdis={Rdis}
E_ABM9 VREF 0 VALUE { MIN(V(SS_INT) ,{VREF_VAL}) }
.ENDS Softst_Gen
*
*$
.subckt Softst_Gen_S1 1 2 3 4 PARAMS: Rdis=3k
S_S1 3 4 1 2 _S1
RS_S1 1 2 1G
.MODEL _S1 VSWITCH Roff=1e9 Ron={Rdis} Voff=0.2 Von=0.8
.ends Softst_Gen_S1
*
*$
.model D_Dsoftstart d is=1e-015 tt=1e-011 rs=0.5 n=0.1
*$
.SUBCKT SRLATCHNOP_BASIC_NEW Q Qb R S PARAMS: ic=1 thresh=2.5 vdd=5 vss=0
C_C1 Q 0 1n IC={IC}
C_C2 0 QB 1n
E_ABM5 N00055 0 VALUE { if(v(R) >{THRESH}& v(S)<{THRESH},{VSS}, if(v(S)>{THRESH} & v(R)<{THRESH},{VDD},V(Q))) }
R_R1 N00055 Q 1
E_ABM6 N14322195 0 VALUE { IF(V(Q)<{THRESH},{VDD},{VSS}) }
R_R2 N14322195 QB 1
.ENDS SRLATCHNOP_BASIC_NEW
*
*$
.SUBCKT Counter CLK COUNT_FE COUNT_RE GND RESET RST_INT PARAMS: min_pw=10n count_rst=128
R_R4 N16838390 N16838391 {MIN_PW/2}
R_R5 N16842332 CLKRE 1
C_C5 GND CLKRE 1n
R_R3 RST_INT N16832011 1
E_ABM4 N16813271 0 VALUE { IF(V(RESET)>0.5 | V(RST_INT)>0.5,0,IF(V(CLKRE)>0.55,V(COUNT_FE)+1,V(COUNT_RE))) }
R_R6 N168433471 CLKI 1
E_ABM6 N16832011 0 VALUE { if(v(COUNT_RE) < 10m,0,if(v(COUNT_FE)> {COUNT_RST}-0.1,1, V(RST_INT))) }
C_C1 GND COUNT_RE_INT 1n IC=0
C_C6 GND CLKI 1n
C_C3 GND RST_INT 1n IC=0
E_ABM10 N168433471 0 VALUE { IF(V(CLK)<0.5,1,0) }
R_R1 COUNT_FE_INT N33733 1
E_ABM8 N16840706 0 VALUE { IF(V(RST_INT)<0.5,1,0) }
C_C4 GND N16838391 1.443n
E_E4 COUNT_RE GND COUNT_RE_INT GND 1
R_R2 COUNT_RE_INT N16813271 1
E_ABM2 N33733 0 VALUE { IF(V(RESET)>0.5 | V(RST_INT)>0.5,0,IF(V(CLKI)>0.55,V(COUNT_RE_INT),V(COUNT_FE))) }
E_E3 COUNT_FE GND COUNT_FE_INT GND 1
C_C2 GND COUNT_FE_INT 1n IC=0
E_ABM7 N16838390 0 VALUE { IF(V(CLK)<0.5,1,0) }
E_ABM9 N16842332 0 VALUE { IF(V(N16838391)>0.5,0,IF(V(CLK)>0.5 & V(N16840706)>0.5,1,0)) }
.ENDS Counter
*
*$
.SUBCKT SRLATCHRHP_BASIC_NEW Q Qb R S PARAMS: ic=1 thresh=2.5 vdd=5 vss=0
¥1 LH LL Q Qb S R ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ SR-FLOP REF=thresh-vss Rout=1m IC=ic
V1 LH 0 vdd
V2 LL 0 vss
.ENDS SRLATCHRHP_BASIC_NEW
*
*$
.SUBCKT Rising_Falling_edge_delay Falling_edge_delay Input_signal Rising_edge_delay PARAMS: Rising_Edge_Delay=0 Falling_Edge_Delay=0
E_ABM3 INPUT_SIGNAL1 0 VALUE { IF(V(INPUT_SIGNAL) > 0.5, 1 , 0) }
X_U20 INPUT_SIGNAL1 N00998 d_d1_REFE
R_R2 INPUT_SIGNAL1 N00998 1.443
X_U16 N00150 Rising_edge_delay BUF_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_C2 0 N00998 {Falling_Edge_Delay}
X_U17 N00998 Falling_edge_delay BUF_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U19 N00150 INPUT_SIGNAL1 d_d1_REFE
R_R1 INPUT_SIGNAL1 N00150 1.443
C_C1 0 N00150 {Rising_Edge_Delay}
.ENDS Rising_Falling_edge_delay
*
*$
.subckt d_d1_REFE 1 2
d1 1 2 dd1
.model dd1 d is=1e-015 tt=1e-011 rs=0.05 n=0.01
.ends d_d1_REFE
*
*$