I have found an interesting bug. If I add a verilog block to a schematic, add all the required pins, and put the code in, everything appears to work fine. But when one pin gets added, the wrong verilog file nets go to the io pins defined in the verilog code. I tried synchronizing the order of pins in the verilog sensitivity list with the netlist order, but no luck.
I have discovered that if I delete all the .cpp, .h, and all non source files from the project, then ventilate the verilog code, everything works perfectly again.
Thanks! That is a complicated, but since I am not editing the c files the verilator generates, I guess using a batch file to delete the verilator output files before verilating, solves the problem for me.
Just got a 3 level flying cap power converter (with closed loop flying cap balancing) using an FPGA to work in simulation, with an efficiency of 98.6% when operating near the 2:1 voltage conversion ratio. I had done the same in LTspice 4 years ago, but the Verilog is so much nicer (and more functional) that a few hundred gates drawn in spice. The Qorvo FETs built into the simulator are nice, and are likely to remain in the final design.