Bus notation from verilog to QSPICE

[EL34]

I’m happy to help!

In addition to my last post, I have one more note to share.
Whenever I changed any port data type, I recreated the ‘Verilog .DLL C++ main template’.
Verilog sources are converted to ‘C/C++’ sources by ‘Verilator’, so it seems that we must update not only the Verilog source but also the ‘Verilog .DLL C++ main’.

Related topic is:

Verilog symbol looses pin synchronization with the verilog code after adding a pin

I have found an interesting bug. If I add a verilog block to a schematic, add all the required pins, and put the code in, everything appears to work fine. But when one pin gets added, the wrong verilog file nets go to the io pins defined in the verilog code. I tried synchronizing the order of pins in the verilog sensitivity list with the netlist order, but no luck. I have discovered that if I delete all the .cpp, .h, and all non source files from the project, then ventilate the verilog code, ev…