This is a simplified COT (constant on-time) Buck converter and I was trying to make the loop gain plot (I knew it might not be a minimum-phase system or whatsoever, just being curious).
In your FRA analysis, it appears that you are using a constant amplitude perturbation source from 1k to 100kHz. From the FRA plot, the gain rolls off quickly when the frequency exceeds 20kHz. If I simulate a .tran with a 30kHz 100mV perturbation, the gating is in burst mode. With such a condition occurs, you might obtain an incorrect result from .bode
Simulating this circuit with .bode is very challenging.
I have to remove IC=0 in C2, as it seems to trigger a bug again (I will report this to Mike).
It cannot use a constant perturbation source because this circuit has a very high gain (>60dB) before 3kHz, and it easily becomes overdriven above 10kHz. What I need to do is apply a high level of perturbation at low frequencies to get enough signal level from V(pert) for analysis and a low level at high frequencies to prevent saturating the controller or causing the inductor current to become discontinuous. Therefore, I added BodeLoPow ,BodeHiPow and set BodeAmpFreq to force a suitable perturbation signal.
This is the simulation result from .bode, without the drop in gain above 20kHz as explained in the first part. buck_cot-3.qsch (19.8 KB)
Indeed, the IC setting of the output capacitor was still causing problems. And the “high gain” + “mode change” is overlooked in my previous simulation.
However, the last result you gave in buck_cot-3.qsch indicates the bandwidth is above 100kHz which may be incorrect. Guess the root cause is the perturbation signal rolls off too fast at 100kHz: (100kHz / 1kHz) ^ (-0.8) * 500mV ≈ 22mV, and this is close to the output ripple which is required to make the system work. When I change the perturbation frequency characteristics to
Again, had to say the converter model is not well defined…
In addition, another problem was found when I tried to compare the simulation of QSPICE to LTspice:
in QSPICE, when a 20pF capacitor is placed in parallel to S1, and when the maximum time step is unlimited (using .tran 12m instead of .tran 0 12m 0 10n), an oscillation at the sw node was observed, which in turn drives the output v(out) to half of the input voltage, 6V. It seems the Buck diode D2 fails to keep conducting even when i(L1) is 10A with small ripples.
in LTspice, with same ideal voltage controlled switch and diode models used, no matter what capacitance is placed in parallel to S1 or D2, the circuit works as expected.
Thanks again, @KSKelvin . It now reminds me of some self-made simulation program years ago, such ringings were also observed and a general solution was to stamp the circuit with Gear method or to hard code the piecewise linear behavior of switching circuits
