This is my understanding: Trapezoidal ringing may occur in simulations with ideal components, and its appearance suggests that practical circuits may experience ringing under practical conditions. I observed that this ringing commonly occurs when simulating circuits with an inductor and diode, particularly when the inductor current reaches zero (which is also when the ringing starts in your simulation).
As far as I know, there are three methods to deal with trapezoidal ringing:
- Reduce timestep at breakpoints: This method involves reducing the timestep, nothing change in your circuit.
- Add damping in the integration to dampen the numerical oscillation: This method requires adding damping elements to the circuit.
- Post-processing data (Modified Trap): Mike proposed this method in LTspice, which is a post-processing approach (you can find more information in the LTspice help). However, Mike did not implement this method in Qspice, and based on discussions in this forum, it seems that Mike no longer wants people to be unaware of trapezoidal ringing.
By understanding these three methods, you should be able to differentiate between each approach:
- Reduce trtol: This affects the timestep strategy and corresponds to method 1.
- Trap with feather: This is a method used in HSpice to detune the trap integration and is possibly related to method 2.
- Gear integration: This essentially changes the integration method, moving away from trapezoidal integration. Gear integration introduces artificial damping, but it is less accurate than trapezoidal integration. This is method 2.