Fatal Error: Timestep too small (after reaching steady state?)

The circuit being simulated is an AC-to-DC subsystem comprised of: 1) AC source with Rs, 2) bridge rectifier (with 2 NMOS FETs as synchronous rectifiers to improve efficiency) 3) bulk filter cap, and 4) macro model for a buck converter, and 5) a constant power current source for load. I am operating on the “low power” side of MPP, which should be stable. Anyway, the transient waveform shows no sign of instability. It appears to have reached steady state, and then BAM! Fatal error occurs.


It truly seems to be an issue with QSPICE’s solver, as opposed to a circuit issue.

Upload you schematic to let us review what can be done. Timestep is too small is common in Spice simulation and not necessary relate to stability but more about I-V is too steep. Or search this forum, we post general direction in resolve timestep too small issue.

Thing to try include

  1. use 80 bits math solver with this directive .option fastmath=0.
  2. limit maximum timestep with directive .option maxstep=<value>. Sometime you need a smaller timestep to help convengence.
  3. change trtol for timestep control. It is hard to say set it loose or tighten can help. .option trtol=<value>.
  4. increase transient iteration limit with .option itl4=<value>
  5. change integration methed, try gear insteat of trap with directive .option method=gear

Other method include gshunt, cshunt, reltol, smooth switch with negative Vh etc…
Don’t be surprise by timestep is too small error, everyone plays with SPICE-based simulator and experience that.