What triggers a C-block to run?

[kgaler]

During an iteration, what triggers the code in a C-block to run? Is it immediately after all its inputs are updated?

Ken

[KSKelvin]

The DLL block processes at each time step. For example, this block only consists of an output port “time” and can return results.

It may be important to note that when using the Ø-Device, the output is returned with one time step delay. (i.e. simulation time step, which can be adaptive)

[kgaler]

I’m talking about when it runs within the step. I’m not sure if I need to know but I’m trying to understand the process. During a .tran, for instance, for every step, there must be a huge list of calculations that need to be run. This list could include one or more c-blocks. I imagine that a code block is treated like a node and each node is calculated sequentially starting at the sources.

So, for each step, does the block run only after all its inputs are updated or arbitrarily and the inputs could be values from the previous step?

Regards,
Ken

[RDunn]

Hi, kgaler.

If I understand your question correctly, it works like this (after a bit of start-up initialization at sim time == 0):

1. QSpice calculates/selects a next simulation timepoint.
2. QSpice calls the DLL MaxExtStepTime() function (if present). If that returns a value smaller than #1, the step is reduced to that value.
3. QSpice calculates all of the circuit values used as inputs to the DLL.
4. QSpice calls the DLL Trunc() function (if present) with the precalculated timestep and input data values.
5. If Trunc() returns a value in *timestep that is less than the step used for #3/#4, QSpice reduces the next timepoint and goes to #3 to calculate new values.
6. At this point, Trunc() didn’t reduce the timestep. QSpice calls the evaluation function with the values from #3/#4. QSpice does nothing beyond saving the output values until the cycle repeats at #1.

Hopefully, it’s clear why there’s a delay between input and output as @KSKelvin described.

So, what happens if we have two DLL components and an output of one component (DLL1) is an input to the second (DLL2)?

Assume that DLL1 changes the output at time=t1. DLL2 sees this change at its input at time=t2. Any change in DLL2’s output doesn’t appear in the circuit values until time=t3.

Did that answer your question?

Note: You might want to see the CBlockBasics documents on my GitHub repo.

–robert

[kgaler]

Thanks, that helps. Looking at your repo now. Excellent!
Ken

[KSKelvin]

Here is a supplementary to @RDunn for multiple DLL-blocks timing. This is for demonstration purpose, therefore, there are several trick to force the simulation to run at 0.1s time step.

But again, this is NOT system delay. By changing simulation timestep, they can eventually “looks” overlap. Therefore, this delay is step size dependent, here is reducing maxstep to 10ms and 1ms.

[RDunn]

As always, nice documentation, Kelvin. Thanks.

[physicboy]

That’s right…

The Cblock read the input from previous timestep. Thus the delay.