Verilog output same as analog output?

QSPICE
1

When I graph V(q2), output of a Verilog block, but then also the graph of V(out), which is V(q2) after a few passive components, I get exactly the same graph. Is this expected? What’s going on? I would expect V(q2) to be like an independent voltage source, so the load should not matter.

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image1623×941 101 KB

The input and outputs of the Verilog block are type bit vector.

Thanks,
Joe

2

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