I am trying to write my own I2C slave module in verilog for use in solar power converter within an FPGA. The issue is that the only options for port type in Qspice is input, output and DLL’s GND. The SDA pin needs to be inout, so that it can receive data or drive SDA low. The motives for writing my own I2C slave is so that simulation can use the same verilog code as synthesis, and not to be locked to a specific FPGA vendor due to use of the vendor’s I2C module.
Also, a minor issue that has come about is that Qspice “create verilog template” function creates “input reg” when it should be “input wire”. The synthesis tool required that to be corrected. Correcting it for the synthesis tool also worked in simulation without issue.
I’m not a Verilog guy so take the following with a grain of salt…
Sounds like you need a component tri-state pin. QSpice C-Block/Verilog components have only input/output/DLL GND as you found. (There is a tri-state component but it isn’t directly a component pin/port thing.)
I ran into this problem when creating a generic SPI device and implementing Microchip micro-controllers. I’ll refer you to my QSpice GitHub repo. Specifically, the GPIO, SpiIO, and QMdbSim projects may be of interest. QSpice implements Verilog stuff as C-Block components so the C-Block Basics series may also be of interest.
Hope that helps. Please do share whatever you learn.
Thanks. I see how you solved the problem in GPIO_Test.qsch. Although that would work, it breaks having the same verilog code base running in the FPGA and in Qspice. Right now I have sigma delta ADCs (using LVDS receivers as comparators), PID control loops, a custom variable frequency and idle time PWM controller all running in simulation in Qspice, with the same exact code being compiled to run in a GoWin FPGA, but with a “wrapper” to handle things internal to the FPGA that Qspice would not understand
Inout functionality would greatly simplify FPGA testing. Hope that can be added in a future version of Qspice.
For now, I can probably solve the issue by putting the Inout inside the FPGA wrapper, and making it run in Qspice similar to what you have done.
BTW, looking at the ACT43850-102.qsch demo circuit, a proper ACK is not generated, which would require inout functionality.
Would you like to try sending Mike an email with this request? Maybe he’ll implement it if someone makes him aware of this problem, of this need to have in QSPICE.