Hello everyone,
I am trying to learn verilog in order to make some mixed design simulations in Qspice which can be implemented on real hardware using FPGA. I just encountererd an issue with a test bench that included timing directives. Below is an exerpt of Verilator error report:
%Warning-STMTDLY: tb_memory_controller.v:55:11: Unsupported: Ignoring delay on this delayed statement.
: … In instance tb_memory_controller
55 | always #5 clk = ~clk;
| ^
… For warning description see Errors and Warnings — Verilator 5.046 documentation
… Use “/* verilator lint_off STMTDLY */” and lint_on around source to disable this message.
%Warning-STMTDLY: tb_memory_controller.v:65:6: Unsupported: Ignoring delay on this delayed statement.
: … In instance tb_memory_controller
65 | #10;
| ^~
%Error-UNSUPPORTED: tb_memory_controller.v:69:5: Unsupported: timing control statement in this location
: … In instance tb_memory_controller
: … Suggest have one timing control statement per procedure, at the top of the procedure
69 | @(posedge clk);
| ^
%Warning-STMTDLY: tb_memory_controller.v:71:6: Unsupported: Ignoring delay on this delayed statement.
: … In instance tb_memory_controller
71 | #1 $display(“%0t\t%b\t%b\t%h\t%h\t%h”, $time, we, oe, write_data, data, read_data);
| ^
%Error-UNSUPPORTED: tb_memory_controller.v:72:5: Unsupported: timing control statement in this location
: … In instance tb_memory_controller
: … Suggest have one timing control statement per procedure, at the top of the procedure.
I am not asking any help in debugging this issue but a more general document about what is implemented (or not) in Qspice implemetation of verilog?
Thanks a lot