I get the folowing error while compiling the Verilog code. Any help in resolving this would be of great help.
cd4536b.cpp:
Vcd4536b.cpp:
Vcd4536b__Syms.cpp:
Vcd4536b___DepSet___0.cpp:
Vcd4536b___DepSet___0__Slow.cpp:
Vcd4536b___Slow.cpp:
link cd4536b+Vcd4536b+Vcd4536b__Syms+Vcd4536b___DepSet___0+Vcd4536b___DepSet___0__Slow+Vcd4536b___Slow,cd4536b.dll,verilated+kernel32,cd4536b/noi;
OPTLINK (R) for Win32 Release 8.00.16
Copyright (C) Digital Mars 1989-2013 All rights reserved.
C:\PROGRA~1\QSPICE\dm\bin..\verilator\verilated.lib(verilated) Offset 09062H Record Type 0091
Error 1: Previous Definition Different : _DllMain@12
One common mistake in C++ or Verilog is that while coding, you add, delete, or modify ports in the symbol but forget to rebuild the template or update the port definition.
For Verilog, consider deleting all files except for your Verilog code and schematic, and rebuilding the entire project. Here is the workflow if a new port is added.
After redoing the entire symbol and Verilog code, basically a new simulation file I am getting the following compile error which I have not been able to resolve:
(instance)->set = data[2].b;
** ^* cd4536b_x1.cpp(25) : Error: ‘set’ is not a member of ‘Vcd4536b_x1’, did you mean ‘reset’? cd4536b_x1.cpp: — errorlevel 1
To be noted that CD4536B IC has both ‘reset’ and ‘set’ input pins.
As you are a basic member, you can upload files. Would you mind uploading the .qsch and .v files—the two files required to run your project? I need to take a look at your symbol and code.
Change set to something else (e.g. set0), then recreate the Verilog template and recompile.
I’m not sure why using the keyword set creates this kind of issue.
Thanks for the suggestion. Now the code does compile, however the counter output still remains stuck at 0V. This will require another look at the verilog code.
