Hi guys, I am trying to do a mixed signal simulation of a SAR ADC for which I have verilog code for its controller/SAR logic. I followed the steps described by Mike in this tutorial. Since I already had the file called controller.v with my symbol itself named controller when I clicked open verilog source, Qspice automatically opened the verilog code. Now, I have checked the code with icarus verilog and it doesn’t have any errors according to it. When I compile this verilog code to C++ in Qspice however, I get “controller.v verilated successfully” message at the bottom of my window and then a window pops up which says I have too many C++ errors in the code.
For context, ctrlp and ctrlm are 12 bit vector buses which are output from my controller block. When creating the symbol I made sure to select vector bus as data type with range configured as [11:0] for both of them. And rst is supposed to be a binary reset signal given to my comparator/ output from the controller block (data type as float64 since that’s what Mike selected in the tutorial for an analog input). Can somebody please help me fix this error?