Verilog by example code implementation in QSPICE

QSPICE
1

How would I implement the first Verilog code example (simple_in_n_out) from the Blaine C Readler book in QSPICE?

///////////////////////////////////////////////////
//
// Header information -- details about the context,
// constraints, etc..
//
///////////////////////////////////////////////////
module simple_in_n_out
(
// Inputs
in_1,
in_2,
in_3,
// Outputs
out_1,
out_2
);
// Port definitions
input in_1;
input in_2;
input in_3;
output out_1;
output out_2;
// ------------- Design implementation --------
assign out_1 = in_1 & in_2 & in_3;
assign out_2 = in_1 | in_2 | in_3;
endmodule

I hope it is OK to post this first example here. How do I get started using this code example? Thanks.

2

Hi,

Please check out ‘Using C++ and Verilog in QSPICE’ at the following link:
https://www.qorvo.com/design-hub/videos/using-c-plus-plus-and-verilog-in-qspice.