Verilog block, adding ports not working for .dll symbol type, bug?


I’m trying out the feature of verilog blocks.
Unlike the tutortial sent out with the beta invite, I can’t add new “add ports” once I’ve selected symbol type “.dll”
If I want to add more ports I have to change symbol type and then reselect symbol type to .dll again to define the ports data type and later add it to verilog.

I don’t know if this is just for me or if it’s a bug, I can press “add port” when Symbol Type is .dll but nothing happens, but it works if I change Symbol Type.

Opps. That got broke. Fixed now. Please do an update. Next time you launch QSPICE, it should immediately let you know an update is available.