Hi Robert,
The example I supplied is a minimal testbench to demonstrate the issue.
My end goal is to run a verilator simulation that “has timing”, so wants to execute at discrete time steps of 5 or 10ns. Verilator will tell you when the next timestep is by calling the nextTimeSlot() function - so what I want to do is use the Trunc function to let the analog simulator know my desired next timestep.
I want to co-simulate with analog circuits that have active features that create edges asynchrously and so I want the analog simulator to be able to change timestep to resolve these edges but also to hit the timeslots that Verilator needs.
The c code that I supplied tries to force the simulator to hit time slots exactly every 5ns - this emulates my Verilator simulation. The voltage source on the schematic creates edges every 13ns - this is emulating asynchronous analog stuff. The analog simulator will shorten the timesteps to resolve these edges. I’d expect the Trunc function to respect the minimum timestep that I request - but it doesn’t always do this.
A workaround is to set the voltage source to pulse at 10ns period, but this will add ~10 points at each edge and so slow the sim down by a factor of 10 which is very undesirable.
With thanks
Dale