Tiny (but confusing) bug in DWM1001 module schematics


just reporting a “typo” in the DWM1001 Schematic that misled me a bit on the pin assignments when setting up an uart driver on the nRF52832 for a different OS than eCos[size=x-small][font=Times New Roman Bold] [/font][/size].
Unless I am missing something, on page 2 in the Castellation block:
[]GPIO_13 should be mapped to J1.17 instead of J1.14
]UART_RX should be mapped to J1.18 instead of J1.15


Hi Roudy,

Yes, a new updated schematic with BOM included is about to be released, this issue has been fixed.

In fact the castellation is labeled incorrectly J1.1 to J1.14 on the left side and J1.15 to J1.34 on the right side.
This should be J1.1 to J1.17 on the left side and J1.18 to J1.34 on the right side.


Hi Ken,

that’s cool.
Awaiting patiently for the full R2 ;).


Updated schematics posted here


Hi Kenneth,
Any change list for this please?

Do ww need to tie VDDDIG, even if we are not using status LEDs? (referring to more current requirement)


Will add a change log to next release.
But FYI there is no physical or electrical change to the module, the only changes where ‘cosmetic’, BOM was added, typos fixed and pin names made clearer.

No sure i follow the VDDDIG question/comment. VDDDIG is tied to VDDREG on the module.

About the VDDDIG to VDDREG Tie,
The datasheet suggests that both of these pins are (The same) power out, and need to be individually decoupled.
It goes on to say that if driving current to external LEDs they should be tied together.
If I’m not driving current with the GPIO pins can I leave them disconnected?

It is not clear why current sharing between the pins is a good (or bad) idea, or what size trace is appropriate. The under chip route effectively blocks other IO escape routes and would be nice to avoid if not necessary.
Thanks for your guidance,

Hi Paul,

Yes, it’s not necessarily to connect them together if you are not going to supply high current by GPIOs, just needs to decouple both.

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