Why is the Qorvo SiC JFET temperature coefficient (TC) of on-resistance so high compared to some SiC MOSFETs?
As RDS∙A approaches the theoretical limit, the on-resistance TC approaches that of the SiC material. All MOS gated devices have an inversion layer in the channel that has a negative on-resistance TC. The negative TC of the MOS channel counters the positive TC of the SiC bulk material, resulting in a net lower on-resistance TC for many SiC MOSFETs. Qorvo SiC JFETs have a far lower RDS∙A over the full temperature range, even considering the strongly positive TC of on-resistance.
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