I presume you mean NT2016SA.
Confusingly, this part number seems to come in both a TCXO and a VCTCXO version. The VCTCXO version has a voltage control input that can be used to pull the center frequency from 8 to 13 ppm, either low or high. Generally, you don’t want a VCTCXO since you don’t really want to be off nominal frequency, and the voltage control pin is subject to input noise which degrades the stability of the frequency. Are you using the VCTCXO version?
There are a lot of gotchas when using a TCXO with a DW1000, it is not as simple as one might imagine and many easy ways to screw it up.
We were only getting about 10 feet of range so looked at the output in CW mode (Channel 5) and found high-level spurs spaced at about 550 kHz out to at least 3.3 MHz. We replaced the TCXO with a signal generator and set it to .9 v p-p and everything behaves wonderfully.
The NDK part is identical to your recommended Abracon part in terms of output level and load. But it certainly behaves as if there isn’t enough drive. The TCXO is being driven from an LDO at 1.8 volts. VBATT on the DW1000 IC is being driven from 3.3v, same line as feeds the TCXO LDO.
The layout looks clean and the traces are short. I’d like to avoid a re-spin to put in a logic-level TCXO. Any comments would be appreciated.
This is a common issue. It can be caused by a number of faults.
One thing not mentioned in the NDK datasheet is the phase noise spec. DW1000 requires -132 dBc/Hz at 1 KHz offset, -145 dBc/KHz at 10 KHz offset. Without having a spec from NDK, you do’t know if that is met or not. If it isn’t, you can upset the internal PLLs in the DW1000 leading to corrupted packets. The Abracom part has listed specs for phase noise that meet DW1000 requirements.
The DW1000 XTAL1 input has a sensitivity to noise on VDDBAT rail. If that is tied directly to VDDPA, which is kind of noisy due to pulse generation, then that upsets the clock input on XTAL1. To solve this problem (or at least reduce it), Decawave recommends an LDO be used to regulate VDDBAT down to 3.0 volts, and operate the TCXO from this rail as well. See DW1000 datasheet Figure 37 (Section 8.1) for example circuit.
The LDO is not needed for a crystal since it is floating relative to the rails and thus somewhat isolated from the noise on the rails. This isn’t so for the TCXO. XTAL2 should be left floating.
If you under drive or over drive the XTAL1 input, you create spurs as you have seen in the CW output (and thus corrupts the UWB signal when generated). Anything over about 1.2 Vpp risks generating spurs. Anything under about 0.5 Vpp does that also. These numbers are from our experiments investigating these kinds of issues. Your idea of going to a 3.3 V drive will make things worse, you will definitely get spurs then, and logic signals have faster edge rates which introduce noise.
Layout of the PLL filter parts are important to achieve the best performance. Noise or other problems in that area can disrupt the PLLs.
The number and layout of the ground vias under the DW1000 can have a surprising effect on performance sometimes, too.
When operating with a TCXO, you want to set XTAL_TRIM to the lowest value, least capacitance.
There are also weird TCXO behaviors and issues you can run into. Here’s a post I made describing some of those:
Sorry I can’t give you a simple answer, these kinds of problems are hard to find and solve.
BTW, what is the Zin (R & C) of pin 3 on the DW1000?
That isn’t given in the datasheet.
From the fact it is a crystal input, one can presume it is quite high in impedance with a DC bias network of some kind (hence DC block on external clock source) and probably very low capacitance, just a few pF.
Mike Ciholas, President, Ciholas, Inc
3700 Bell Road, Newburgh, IN 47630 USA
mikec@ciholas.com
+1 812 962 9408