Stepping Simulation Numerical Errors

Hi there,

while evaluating the code for my PI Digital controller, I think i’ve stumbled into some issues regarding (what I think is)stepping parameters. As can be seen in the attached figure, my current design is made of a Laplace plant and a digital controller, which used the CPU_CLK falling edge to execute some code ( a simple PI controller in this case). The issue is that although i’ve clearly selected two identical “delays” between the CPU clock and the reference pulse (placed in t=0), my system responses are not equal.

My guess is that somehow although the transient simulation is itself stepping correctly, the initial conditions of either the controller (.dll) or the SPICE simulation itself are not reseting, which in my point of view should be the correct behaviour.

Sincerely I’m not fully aware if this is some sort of error/bug or if it is the intended behaviour and I’m the one not using the simulator correctly.

Best Regards,
Rodrigo Anjos

Hi, Rodrigo.

Maybe you could post the *.qsch and *.cpp files? Otherwise, I’d just be sending you down rabbit holes with wild guesses.


Hi Robert,

after some digging out, the conclusion that i’ve come to is that in fact, the C++ code does not “reset” after each iteration of the stepped simulation. A simple C++ block with one output mapped to a counter is enought to demonstrate that. To work around this issue i’ve created a behavioral voltage source whose voltage is mapped to the ‘time’ variable internal to the SPICE engine. I fed this time into the C++ block and add a reset if this variable is in fact equals to 0.

if(time == 0){;} // Reset Internal Variables
// Rest of the code

With this approach the system behaves as (at least in my mind) expected. I think that my only question now is if this behaviour is intended in fact, or if it is some sort of bug.
To be honest I’m not realy able to come out with plausible scenarios in which not reseting the C++ code is beneficial. But that’s my little bubble, and I’m sure someone might see some use to this.

P.S. I did not attach either files just because of laziness. If you still wish to investigate theses files @RDunn I would be happy to provide them.

Best Regards,
Rodrigo Anjos

Hi, Rodrigo.

Glad you figured it out. You might want to see the CBlockBasics2.* stuff on my GitHub repo for an approach that doesn’t require an additional schematic component.

BTW, the C-Block will get called with time==0 some five or six times when the simulation starts. Not sure what you’re doing in the reset bit but if multiple calls are a problem, then it’s better to do all initialization in the “initialization section” where per-instance data is allocated since that’s executed only once (see the first CBlockBasics.* stuff).


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@RodrigoAnjos ,

@RDunn is correct. I also have a C-block component called Logger that I’ve provided this forum that has accommodations for multi-instanced components in a multi-stepped sim. You can find it at: New Component: Logger V2.1 [UPDATE]

I hope this helps.