the simulation stop time is 20ms and it takes about 8s cpu time, the CPU usage of QSpice is only 4.5%, any method that can improve the usage of CPU for QSpice?
there’s inductor current imbalance output voltage spikes when do open-loop simulation, how to eliminate the undesired imbance and spikes without reducing the simulation speed?
Thanks a lot, the new results have less current imbalance and voltage spikes, it’s ok for me.
And it really changes a lot:
.opt method=gear trtol2=0
indutor with Rser & Rpar
MOS & D model
timestep
Bad news is the simulation time x2, next i’ll try to speedup the simulation.
The best solution is to run the whole controller and PWM gen within Cblock (assuming you are working with digital control).
I have Made many kinds of digital control smps (interleaved totem pole PFC+DAB), T-Type inverter, LLC converter, etc. And it run almost as fast as Plecs or PSIM.
The only potential problem is… The learning curve is crazy steep.