Hello Qspice Community,
I did the same simulation with LTspice and I got good result (The OUT is around 1.24 V). With Qspice I got an error . Some body ca help me ? Please.
Thank you
Regards,
Davide
tlv431.qsch (3.4 KB)
tlv431_test.qsch (2.4 KB)
tlv431.qsym (676 Bytes)
This is in Hierarchy, copy “tlv431-Hierarchy.qsch” and “tlv431.qsch” in same directory to run the simulation.
tlv431-Hierarchy.qsch (2.5 KB)
tlv431.qsch (3.4 KB)
tlv431.qsym (623 Bytes)
Or, you can have a subckt symbol structure, just copy “Parent.TLV431-SubcktSymbol.qsch” and can run the simulation.
Parent.TLV431.qsch (5.3 KB)
TLV431.qsym (3.4 KB)
Hello KSKelvin,
Thank you for your reply. Yes it works.
Did you change something in spice file ?
I do not understand why it works with your files.
Thank you for your support.
Regards,
Davide
No change in spice netlist. Originally, your symbol is in hierarchy syntax, i.e. nothing is defined in Type.
The major problem is that you have two repeated attribute with TLV471, and correct should only have one. In addition, your child schematic net name incorrectly match your auto created symbol net name.
However, your original method using a hierarchy symbol call a child schematic contain an auto generated symbol just a tedious way in this case, and I simplified it back to a single symbol with .subckt included. Copy the one line .subckt generated in auto generated symbol, paste it into your created symbol and deleted the duplicated TLV471 attribut line.
Thank you KSKelvin !
Davide