Hello, I’ve followed along in the forum here about running third party models.
I downloaded spice package for CBB011M12GM4 full bridge. The package comes with LTspice, PSpice, and Simetrix files. I created a test bench for both the module and individual mosfet, using the PSpice file, which are attached. The bare mosfet runs OK, but the module has minimum time step convergence issues. Can anyone get the module test bench to run any better? I tried without fastmath already.
CB011M12GM4.qsym (5.3 KB)
CBB011M12GM4.lib (15.0 KB)
CBB011M12GM4T_test1.qsch (31.4 KB)
CBB011M12GM4T_test2.qsch (18.1 KB)
mosfet.qsym (870 Bytes)
Quick solution for your CBB011M12GM4T_test1.qsch, change .tran num_period/frq to .tran num_period/frq skipbp, to start with all FET turn off.
The problem is that, I forgot to handle the initial condition in PWM-Complementary.qsym. One output is high and one output is low at t=0s if duty at 0s is non-zero, which is not friendly for switching mode power supply simulation.
I just modified this symbol and updated in my Github, to force both output to Vlow at t=0s (Vhigh and Vlow are hidden attribute in this symbol).
Just a remind, when you auto generate symbol for CB011M12GM4, you forgot to select “Include Entire File”, all dependent subcircuit will not be included in the embedded subckt and therefore, you still need to link to an external library. Here is a complete version with all subcircuit included, and with the modified PWM symbol with initial condition to force OUTA and OUTB to low at t=0s.
CB011M12GM4.qsym (15.1 KB)
CBB011M12GM4T_KSK.qsch (38.2 KB)
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