Hi, I’m a new QSPICE user, trying to simulate an LTSPICE netlist with no luck.
I added missing .lib files and added .plot V(VA), etc. lines to the netlist file.
When I click on the Run button, there are no errors, but nothing shows up in the Output Window.
What am I missing?
I’ve attached my LTSPICE netlist below:
* E:\Users\foo\LTSpice\LED_Driver\Simple_with_Cable_LR_+IR_Limiter\LED_Driver.asc
* Generated by LTspice 26.0.0 for Windows.
VDD VDD 0 5V
VLED VLED 0 PWL(0 0V 1ms 6V)
R1 G N010 47
R2 S 0 1
R3 N002 N003 4
D1 VA VC 1N4007
C1 N003 0 470µF V=10 Irms=1.4 Rser=0.1 Lser=0 mfg="Vishay" pn="T97H477M010" type="Tantalum Conf Coat"
R4 NIDAQ_AO N012 40.2K
R5 N012 0 10K
D2 0 N012 1N4148
C2 N012 0 10pF
C4 N014 0 220nF
R6 G N014 10
VSRC NIDAQ_AO 0 PULSE(0V 5V 50ms 1us 1us 100us 10ms)
C3 N010 N009 1pF
L1 N003 N007 1.1µH
X§U2 VC G S FET_TEMP FDT439N ;§pnba D)G)S)T
R7 N007 VA 0.65
R8 N011 N004 100
X§U1 N011 N009 VDD 0 N010 VDD ADA4805 ;§pnba 100)101)102)103)104)106
R9 N008 N004 100
X§U3 N008 0 VDD 0 NC_01 VDD ADA4805 ;§pnba 100)101)102)103)104)106
R10 N006 N004 100
X§U4 N006 0 VDD 0 NC_02 VDD ADA4805 ;§pnba 100)101)102)103)104)106
R11 N005 N004 100
X§U5 N005 0 VDD 0 NC_03 VDD ADA4805 ;§pnba 100)101)102)103)104)106
R12 N004 0 1G
R13 S N009 6.8K
X§U6 N012 N004 VDD 0 N004 ADA4084-2 ;§pnba In+)In-)V+)V-)OUT
C5 N003 0 470µF V=10 Irms=1.4 Rser=0.1 Lser=0 mfg="Vishay" pn="T97H477M010" type="Tantalum Conf Coat"
C6 N003 0 470µF V=10 Irms=1.4 Rser=0.1 Lser=0 mfg="Vishay" pn="T97H477M010" type="Tantalum Conf Coat"
C7 N003 0 470µF V=10 Irms=1.4 Rser=0.1 Lser=0 mfg="Vishay" pn="T97H477M010" type="Tantalum Conf Coat"
R14 N002 N003 4
R15 N002 N003 4
R16 N002 N003 4
R17 VLED N002 2
X§U7 N002 N001 VLED NC_04 NDT456P ;§pnba D)G)S)T
R18 N001 VLED 100K
R19 0 N001 20K
C8 VLED N001 1µF V=10 Irms=1.4 Rser=0.1 Lser=0 mfg="Vishay" pn="T97H477M010" type="Tantalum Conf Coat"
.model D D
.lib C:\Users\techie\AppData\Local\LTspice\lib\cmp\standard.dio
.option ITL4=200 Gmin=1e-11 Abstol=1e-10 Trtol=4 Chgtol=1e-10 MinDeltaGmin=0.0001
*.options cshunt=1e-15
.ic V(C1)=0 V(C5)=0 V(C6)=0 V(C7)=0 V(C8)=0
.tran 70ms uic
* Differential Loop Inductance = 220nH / ft.\nof 28AWG twisted pair wires w/\n0.8mm spacing.
* BAC: 5ft. max.\ncable length
* NI DAQ slew rate = 5V/us
* AD8605:\n1K, 47, 33nF\n33, 12, 470nF\n \nADA4805:47, 10, 220nF
* 28AWG Cable Resistance = 0.065 Ohms / ft.\nRloop = 0.13 Ohms / ft.
* 10V::2A\n5V::1A
* Chgtol must be >= 1e-10 for stability
* Series Current Limiting Resistor\ncharges flash cap in 5*tau = 10ms
* Library below included based on ModelFile attribute of instance X§U6 (C:\Users\techie\AppData\Local\LTspice\lib\sym\OpAmps\ADA4084-2.asy)
.lib ADA4084-2.lib
* Library below included based on ModelFile attribute of instance X§U1, X§U3, X§U4, X§U5 (C:\Users\techie\AppData\Local\LTspice\lib\sym\OpAmps\ADA4805.asy)
.lib ADI.lib
* Library below included based on ModelFile attribute of instance X§U2 (E:\Users\techie\Vivonics\Active Projects\2160 BAC PhII\POC\LTSpice\LED_Driver\Simple_with_Cable_LR_+IR_Limiter\FDT439N.asy)
.lib FDT439N.ckt
* Library below included based on ModelFile attribute of instance X§U7 (E:\Users\techie\Vivonics\Active Projects\2160 BAC PhII\POC\LTSpice\LED_Driver\Simple_with_Cable_LR_+IR_Limiter\NDT456P.asy)
.lib NDT456P.ckt
.plot V(VA), V(VC)
.backanno
.end