QSPICE Schematic Capture (Verilog Counter)

[mccunets]

For this week’s QSPICE schematic capture, we have “Verilog Counter,” one of the demonstration ones Mike created to show various QSPICE features and capabilities. (Schematic Capture Post #043) For more on using C++ and Verilog in QSPICE®, please check out this video: HowToC++
VerilogCounter.qsch (3.5 KB)

[MikeKi]

Hello! I don’t quite understand if it is possible to use signed registers in verilog? The OUT signal does not want to take negative values..