Qspice cant get Verilog to output anything besides 0V

Hi Robert_1,

I think this issue might be related to the *.cpp file.

Whenever I modify my Verilog code, I delete the *.cpp file and rebuild the project.
That seems to solve the issue.

It looks like the *.cpp file doesn’t get updated when I rebuild after modifying the Verilog code. Even though the *.DLL file is refreshed, the *.cpp file remains unchanged.

I’m not sure if this is the actual cause of the issue, but I’ve found that manually deleting the *.cpp file is necessary whenever I make changes to my Verilog code

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