The QPB9350 (Rev.G) datasheet indicates that the minimum period of the SCLK is 50ns, suggesting that it can operate with an SCLK of 20MHz. Our circuit uses the suggested pull-up resistor value on the SDO pin of 4.7kΩ to VDD_SPI. An oscilloscope probe attached to the SDO pin shows the SDO signal rising with a waveform that looks like an RC step response, however, with 4.7kΩ the SDO pin doesn’t rise fast enough for the SCLK to even be 1MHz. It seems to run reliably at about 625kHz.
Questions:
- Is the SDO pin an open-drain output as implied by the oscilloscope’s waveform?
- Although the datasheet recommends 4.7kΩ for the SDO pin’s pull-up resistor, we might want a lower value to get a faster rise time and run SCLK faster. What is the strongest pullup resistor you recommend for the SDO pin? Another way to ask the same question: what is the maximum recommended current for the SDO pin to sink and still reliably achieve the datasheet’s 0.3V output voltage? I can’t seem to find this information in the datasheet.
- Can you provide a ballpark capacitance value for the SDO pin?
Thanks in advance,
Chris