Hello,
I am working with QM33110W and I have some problems with the SPI CRC.
Below are the exchange logs.
Turn on CRC control:
0:00:00.022 UWB: SPI CRC check enabled
0:00:00.022 SPI2: wr(2) c041
0:00:00.022 SPI2: wr(2) ff40
0:00:00.022 SPI2: wr(2) 4040
0:00:00.022 SPI2: rd(4) c8010000
0:00:00.022 SPI2: wr(2) 4060
0:00:00.022 SPI2: rd(1) cf
0:00:00.022 QM33110: CRC calc 0xcf read 0xcf
0:00:00.023 UWB: SYS_CFG=000001c8
Reading the DEV_ID register using short addressing causes a CRC error:
0:00:00.024 SPI2: wr(1) 00
0:00:00.024 SPI2: rd(4) 0403cade
0:00:00.024 SPI2: wr(2) 4060
0:00:00.024 SPI2: rd(1) c6
0:00:00.024 QM33110: CRC calc 0x9e read 0xc6
0:00:00.024 UWB: SPI read CRC error
0:00:00.024 SPI2: wr(2) 4110
0:00:00.024 SPI2: rd(4) 00000000
0:00:00.025 SPI2: wr(2) 4060
0:00:00.025 SPI2: rd(1) 6d
0:00:00.025 QM33110: CRC calc 0x6d read 0x6d
0:00:00.025 UWB: status_lo=00000000
0:00:00.025 SPI2: wr(2) c110
0:00:00.025 SPI2: wr(4) 00000000
0:00:00.025 SPI2: wr(1) 81
Reading the DEV_ID register using full addressing works fine:
0:00:00.024 SPI2: wr(2) 4000
0:00:00.024 SPI2: rd(4) 0403cade
0:00:00.024 SPI2: wr(2) 4060
0:00:00.024 SPI2: rd(1) e8
0:00:00.024 QM33110: CRC calc 0xe8 read 0xe8
0:00:00.024 SPI2: wr(2) 4110
0:00:00.024 SPI2: rd(4) 00000000
0:00:00.025 SPI2: wr(2) 4060
0:00:00.025 SPI2: rd(1) 6d
0:00:00.025 QM33110: CRC calc 0x6d read 0x6d
0:00:00.025 UWB: status_lo=00000000
0:00:00.025 SPI2: wr(2) c110
0:00:00.025 SPI2: wr(4) 00000000
0:00:00.025 SPI2: wr(1) 81
Reading and writing the DEV_CFG register using full addressing works fine. And register SYS_CFG does not change its contents:
0:00:00.025 SPI2: wr(2) 4040
0:00:00.025 SPI2: rd(4) c8010000
0:00:00.026 SPI2: wr(2) 4060
0:00:00.026 SPI2: rd(1) cf
0:00:00.026 QM33110: CRC calc 0xcf read 0xcf
0:00:00.026 UWB: SYS_CFG=000001c8
0:00:00.026 SPI2: wr(2) c040
0:00:00.026 SPI2: wr(4) c8010000
0:00:00.026 SPI2: wr(1) 23
0:00:00.026 SPI2: wr(2) 4040
0:00:00.027 SPI2: rd(4) c8010000
0:00:00.027 SPI2: wr(2) 4060
0:00:00.027 SPI2: rd(1) cf
0:00:00.027 QM33110: CRC calc 0xcf read 0xcf
0:00:00.027 UWB: SYS_CFG=000001c8
0:00:00.027 SPI2: wr(2) 4110
0:00:00.027 SPI2: rd(4) 00000000
0:00:00.027 SPI2: wr(2) 4060
0:00:00.027 SPI2: rd(1) 6d
0:00:00.028 QM33110: CRC calc 0x6d read 0x6d
0:00:00.028 UWB: status_lo=00000000
0:00:00.028 SPI2: wr(2) c110
0:00:00.028 SPI2: wr(4) 00000000
0:00:00.028 SPI2: wr(1) 81
Modification of the DEV_SFG register using a 4-bytes masked write transaction results in modification of the low byte of the register with the value of the CRC byte. The AND mask FFFFFFFF and OR mask 0000000 are used. There is no CRC error.
It can be assumed that the CRC byte is added to the command data: FFFFFFFF:0000000 + 52 → FFFFFF00:0000052
0:00:00.028 SPI2: wr(2) 4040
0:00:00.028 SPI2: rd(4) c8010000
0:00:00.028 SPI2: wr(2) 4060
0:00:00.029 SPI2: rd(1) cf
0:00:00.029 QM33110: CRC calc 0xcf read 0xcf
0:00:00.029 UWB: SYS_CFG=000001c8
0:00:00.029 SPI2: wr(2) c043
0:00:00.029 SPI2: wr(8) ffffffff00000000
0:00:00.029 SPI2: wr(1) 52
0:00:00.029 SPI2: wr(2) 4040
0:00:00.029 SPI2: rd(4) 52010000
0:00:00.030 SPI2: wr(2) 4060
0:00:00.030 SPI2: rd(1) 05
0:00:00.030 QM33110: CRC calc 0x05 read 0x05
0:00:00.030 UWB: SYS_CFG=00000152
0:00:00.030 SPI2: wr(2) 4110
0:00:00.030 SPI2: rd(4) 05000000
0:00:00.030 SPI2: wr(2) 4060
0:00:00.030 SPI2: rd(1) 23
0:00:00.030 QM33110: CRC calc 0x23 read 0x23
0:00:00.030 UWB: status_lo=00000005
0:00:00.030 SPI2: wr(2) c110
0:00:00.031 SPI2: wr(4) 05000000
0:00:00.031 SPI2: wr(1) cf
2-byte and 1-byte mask write transactions behave similarly.
Thank you!