Problem with the WMK36N65C4 model

Hi everyone, I’m working on my first custom MOSFET model, following a tutorial step-by-step. However, I’m running into a significant issue with the gate charge calculation.

When I run the simulation, it fails with a fatal error: Fatal error: Timestep too small (1.25244e-19) at t=1.95125e-09.

When I attempt to port this model into QSPICE, the simulation becomes extremely sluggish and produces unphysical results. I suspect the issue might lie in how I’ve defined the capacitances or the gate charge parameters in the .model statement.

Could someone help me identify what might be causing this convergence failure and how to resolve it?

.model WMK36N65C4 VDMOS Rs=30m Rd=30m Rg=0.1 Vto=4.35 + Kp=47.4 lambda=16.9m RonX=0.203 eta=75m Vtotc=-2m Is=7.78p + N=1.02373 Rb=5.7m Eg=3.26 XTI=3 Cgs=1.98n Cgdmin=53.7p + Cgdmax=2.63n Cjo=10 tt=240n Tnom=25 mfg=“WAYON” Vds=700 + Ids=32 Ron=80m Qg=46n

Cjo with 10F doesn’t make sense, this is zero bias junction capacitance of body diode. Verify what you have filled in for Zero-biased Output Cap.[F] in the Priminaries tab.