PMSC_CTRL0 Bits8-15

Hello,

is it possible to give an explanation of the undocumented Bits 8-15 of the PMSC_CTRL0 register? Those bits are manipulated in _dwt_enableclocks (e.g. FORCE_LDE sets them to 0b00000011) - but the user manual only describes Bit 10 (ADCCE) and 15 (AMCE).
Why do I have to write the lower byte fist? Is there an explanation in the user manual, I missed?

Thank you!
/Daniel

Am 18.04.2017 um 16:04 schrieb Daniel Augustin:

My Low-Level driver uses these structures for PMSC:

typedef enum { // radio_dw1000_pmsc_state_e - Current PMSC State Machine value
rdps_INIT, // DW1000 is in INIT state
rdps_IDLE, // DW1000 is in IDLE state
rdps_TX_WAIT, // DW1000 is waiting for delayed transmit
rdps_RX_WAIT, // DW1000 is waiting for delayed receive
rdps_TX, // DW1000 is transmitting
rdps_RX, // DW1000 is receiving
rdps_Unknown // unknown/ illegal values below
} radio_dw1000_pmsc_state_e;

typedef enum { // radio_dw1000_rx_state_e - Current Receive State Machine value
rdrs_IDLE, // receiver is idle
rdrs_START_ANALOG, //
rdrs_RX_RDY, //
rdrs_PREAMBLE_FOUND, //
rdrs_PRMBL_TIMEOUT, //
rdrs_SFD_FOUND, //
rdrs_CNFG_PHR_RX, //
rdrs_PHR_RX_STRT, //
rdrs_DATA_RATE_RDY, //
rdrs_DATA_RX_SEQ, //
rdrs_CNFG_DATA_RX, //
rdrs_PHR_NOT_OK, //
rdrs_LAST_SYMBOL, //
rdrs_WAIT_RSD_DONE, //
rdrs_RSD_OK, //
rdrs_RSD_NOT_OK, //
rdrs_RECONFIG_110, //
rdrs_WAIT_110_PHR, //
rdrs_Unknown // unknown/ illegal values below
} radio_dw1000_rx_state_e;

typedef enum { // radio_dw1000_rx_state_e - Current Receive State Machine value
rdts_IDLE, // transmitter is idle
rdts_PREAMBLE, // transmitting preamble
rdts_SFD, // transmitting SFD
rdts_PHR, // transmitting PHY Header
rdts_SDE, // transmitting PHY Header parity SECDED bits
rdts_DATA, // transmitting data block
rdts_RSP_DATA, // transmitting Reed-Solomon parity block
rdts_TAIL, // transmitting tail bits
rdts_Unknown // unknown/ illegal values below
} radio_dw1000_tx_state_e;

typedef union { // register SYS_STATE 0x19:00 System State Information (not described in DW1000 User Manual)
u32_t Word;

struct { 
    radio_dw1000_tx_state_e   TX_STATE;   // Current Transmitter State Machine value -> radio_dw1000_tx_state_e 
    radio_dw1000_rx_state_e   RX_STATE;   // Current Receiver State Machine value    -> radio_dw1000_rx_state_e 
    radio_dw1000_pmsc_state_e PMSC_STATE; // Current PMSC State Machine value        -> radio_dw1000_pmsc_state_e 
} __attribute__( ( packed ) ) Fields; 

} radio_dw1000_register_sys_state_u;

It is part of a complete RTLS solution (OS + Development Environment) for Cortex-M3.
-> http://thetoolchain.com
More documentation on it will follow.

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Mit freundlichen Gruessen,
With kind regards,
Muy atentamente le saluda,

Gregor Rebel
(Dipl. Informatiker / Master of Computer Science)

University of Applied Sciences Munster
Lab for Semiconductor Devices & Bussystems
Stegerwaldstrasse 39
D-48565 Steinfurt
Office +49(0)2551 9 62209
mailto:gregor@fh-muenster.de

Universidad de Granada
E.T.S. de Ingenierías Informática y de Telecomunicación
mailto: gregorrebel@correo.ugr.es

Hey Gregor,

thank you for your answer but unfortunately this isn’t helping me out. PMSC_CTRL0 is used to set the clocks - the SDK manipulates bits that are not documented in the user manual. I was hoping, that someone of decawave may reveal those undocumented bits for me.

/Daniel

Oh sorry, maybe you’re interested in these:

typedef union { // register PMSC_CTRL0 0x36:00 -> DW1000 User Manual p.180
u32_t Word;

struct { 
    unsigned SYSCLKS   : 2; // system clock source      -> radio_dw1000_clock_input_e 
    unsigned RXCLKS    : 2; // receiver clock source    -> radio_dw1000_clock_input_e 
    unsigned TXCLKS    : 2; // transmitter clock source -> radio_dw1000_clock_input_e 
    unsigned FACE      : 1; // Force Accumulator Clock Enable 
    unsigned reserved1 : 2; 
    unsigned OTP       : 1; //? 
    unsigned ADCCE     : 1; // Analog-to-Digital Converter Clock Enable (IC-temperature and input battery voltage) 
    unsigned reserved2 : 4; 
    unsigned AMCE      : 1; // Accumulator Memory Clock Enable 
    unsigned GPCE      : 1; // =1: enable GPIO CLocks 
    unsigned GPRN      : 1; // =0: activate GPIO Reset 
    unsigned GPDCE     : 1; // =1: enable GPIO interrupt input debounce filter 
    unsigned GPDRN     : 1; // =0: activate GPIO debounce reset 
    unsigned reserved3 : 3; 
    unsigned KHZCLKEN  : 1; // =1: enable divider to provide kilohertz clock 
    unsigned reserved4 : 4; 
    unsigned SOFTRESET : 4; // reset sequence: set SOFTRESET to 0b0000, 0b1111 (one after another) 
} __attribute__( ( packed ) ) Fields; 

} radio_dw1000_register_pmsc_ctrl0_u;

typedef enum { // valid values for radio_dw1000_register_pmsc_ctrl1_u.Fields.PKTSEQ -> DW1000 User Manual p.183
rd_pmsc_disable = 0x00, // disable PMSC control of analog RF subsystems
rd_pmsc_enable = 0xe7 // enable PMSC control of analog RF subsystems
} radio_dw1000_pmsc_control_e;

typedef union { // register PMSC_CTRL1 0x36:04 -> DW1000 User Manual p.183
u32_t Word;

struct { 
    unsigned reserved1 : 1; 
    unsigned ARX2INIT  : 1; // 1: automatic transition from RX to INIT state (-> low duty-cycle SNIFF mode) 
    unsigned PKTSEQ    : 8; // -> radio_dw1000_pmsc_control_e 
    unsigned ATXSLP    : 1; // 1: automatically return to sleep after TX (requires valid AON configuration) 
    unsigned ARXSLP    : 1; // 1: automatically return to sleep after RX (requires valid AON configuration) 
    unsigned SNOZE     : 1; // 1: enable SNOOZE mode 
    unsigned SNOZR     : 1; // 1: enable SNOOZE repeat mode (-> low-power listening) 
    unsigned PLLSYN    : 1; // 1: enable special 1GHz clock form some external SYNC modes 
    unsigned LDERUNE   : 1; // 1: enable Leading Edge Detection algorithm (required to update Receive Time Stamp register) 
    unsigned KHZCLKDIV : 6; // top 6 bits of 10-bit kilohertz clock divider (input is 19.2MHz XTI clock) 

} __attribute__( ( packed ) ) Fields; 

} radio_dw1000_register_pmsc_ctrl1_u;

Hey Gregor,

again - thank you for your answer.

Reading your enumeration, I can see that Bit9 is OTP. Where do you have this information from? In the user manual v2.10 (and earlier) this bit is marked as reserved.

The usermanual sais - before loading the LDO-microcode (Page 24 of 227 - v2.10) the PMSC_CTRL0 register needs to be set to 0x0301 (means, that bit 8 and 9 need to be 1). After loading the code, bit 8 needs to be set back to 0. This bit (8) isn’t documented at all.

/Daniel

PS: I can see that the function of the OTP-Bit can be derived by analysing the SDK. Its a bit poor, that it seems not to be possible to set up a running environement without comparing each (own) step with the SDK, because the SDK is based on knowledge one doesn’t get by going through the user manual step by step (which is normally the common way - or at least should be a possible way)

Hi Daniel,

I asked Leo about a year ago.

Hey Gregor,

again - thank you for your answer.

Reading your enumeration, I can see that Bit9 is OTP. Where do you have this information from? In the user manual v2.10 (and earlier) this bit is marked as reserved.

The usermanual sais - before loading the LDO-microcode (Page 24 of 227 - v2.10) the PMSC_CTRL0 register needs to be set to 0x0301 (means, that bit 8 and 9 need to be 1). After loading the code, bit 8 needs to be set back to 0. This bit (8) isn’t documented at all.

/Daniel