Question regarding the PDOA sync circuit of on PDOA beta kit.
The DW1000-Datasheet-V2.09, chapter 5.13 (External Synchronisation) This chapter discusses the minimum time required for the SYNC signal relative to XTAL1. On the rising edge of XTAL1, the sync pulse must be hi at least 10ns before and last at least 10ns after.
On the PDoA Kit Node Miscellaneous Revision 2v2, the clock buffer CLKIN is from a 38.4MHz crystal module. One of the output of the clock buffer goes to each of the DW1000 (XTAL1).
The other output of the clock buffer goes to a NAND gate and then to a flip flop clock input. The output of the flip flop drives the SYNC PIN on each Decawave.
My understanding of the circuit is when the clock transitions form high to low, the flip flop output is driven high until the clock transitions from high to low once more. Given a perfect 0 second propagation delay NAND Gate and flip flop then with a 38.4MHz clock (24ns period) then the SYNC output will stay high for 13ns before the rising edge of the clock and 13ns after the rising edge of the clock and therefore be within the timing constraints of Table 22 (min 10nS either side of the clock high transition).
BUT, NAND gates and flip flops in the real world have delays. For the NAND gate and flip flop used in the PDoA board the maximum propagation delays are 4.3ns and 5.7ns respectively. Therefore worst case after the clock transitions, the output of the flip flop may not transition for 10ns giving only 3ns remaining for the SYNC setup time which is far lower than the required minimum of 10ns.
What am I not understanding?