Passing parameters into a verilog block

[scottishdave]

No, those are ports passing in signals, not parameters.

The type of parameter passing is like that shown in the blog posts on

How to pass a parameter to a C++ module

Hello I am trying to learn how to pass parameters defined as .param into a C++ module but I can’t make it work. Please, see the simple example of the image. Can anyone tell me how to do it or send an example? Thanks! [Untitled]

There’s a few examples for C++…but not for Verilog