Hi all,
I’d like to be able to pass parameters into a verilog block. I see plenty of examples for passing into C++, but I REALLY need to use Verilog.
So far, everything I have tried in verilog seems to be ignored: When I run QSPICE I get
Warning: Ignoring unknown instance parameter “GAINB” of device X2, this implies that whatever I have done in verilog does not result in verilator seeing that there is a parameter.
Does anyone have a verilog code example that works?
Did you try the one from the built in examples? Also, there is a linked video of how to make the Verilog blocks in the help section.
I do not believe there is a built in example that uses verilog and passes in parameters.
I have looked. If you can point me at one, it would be greatly appreciated.
Hi, Dave.
I’m just guessing (I’m not a Verilog guy) but the error suggests that the problem is on the QSpice schematic end. Can you post schematic, code, etc?
–robert
No, those are ports passing in signals, not parameters.
The type of parameter passing is like that shown in the blog posts on
There’s a few examples for C++…but not for Verilog
Example schematic
There are multiple ways of specifying parameters in Verilog, I have tried several of them, in case one works and another does not.
Here’s the current ( non working ) version:
Current version of verilog
Hi, Dave.
GAINB needs a valid data type, i.e., “double GAINB=2.2”. (ROUT doesn’t need a data type because it isn’t a parameter passed to the code.) See “Ø-Device” topic in Help for valid data types.
See if that helps.
–robert
Ah, I see. Just use a voltage source that has a voltage of the parameter. So you would have a voltage source of {GAINB} volts.
I can get rid of the error by adding the type ( thanks ) …but the parameter doesn’t have any effect.
Now I’m finding my verilog doesn’t output anything at all…I’m going to create a new simple verilog and start again… back in a few…
Yeah, Dave, you’ll probably need to regenerate the default templates and add code back. Not being a Verilog guy, I’m not entirely sure of the process. However, this is an issue even for C-Block/non-Verilog stuff.
Please do report back what you find for the benefit of other Verilog users.
Jay,
I’m trying to pass a parameter into verilog. This can be one in c++, so I would hope it is possible in the verilog interface.
Ultimately, the parameter I would like to pass is a probably a string, with multiple values in it.
Something similar to the attributes being used to send I2C data in the QSPICE ACT43850-102 example schematic
See the attributes
Ok, yes there’s all sorts of “do a then b” stuff going on, but this is what I have found:
IF I create a user attribute in the verilog block BEFORE I generate the verilog template as shown below:
Then the verilog template adds an input to the verilog, which is not what I would have expected, nor what want…but it’s what it does ( see input real gaina in code below ).
Hmm, I guess there is no way to pass a parameter into the verilog as a verilog parameter.
Ok, I learned something today.
Thanks all for the help.
I have never used a string data type in Verilog, but it sounds like fun. If you figure it out, let us know.
Strings are supported as a bit of a hack in basic verilog, you can define a very wide register ( 8 bits * number of characters ) and then assign it with a string in quotes, e.g.
reg [8*8:1] stateStr; //reg to hold string
Then assign the value later
stateStr = “POR”;
