Ok, yes there’s all sorts of “do a then b” stuff going on, but this is what I have found:
IF I create a user attribute in the verilog block BEFORE I generate the verilog template as shown below:
Then the verilog template adds an input to the verilog, which is not what I would have expected, nor what want…but it’s what it does ( see input real gaina in code below ).
Hmm, I guess there is no way to pass a parameter into the verilog as a verilog parameter.
Ok, I learned something today.
Thanks all for the help.