Oh, I understand now. You believe the issue is related to the switch model. But trapezoidal ringing is not about the device but about the simulation timestep. That’s why all my focus is on the timestep. An ideal device is the source of trapezoidal ringing in SPICE-based simulators! The more ideal the device, the easier it is to encounter trapezoidal ringing.
Integration (IDT) problem. Why? - QSPICE - Qorvo Tech Forum
An ideal switch allows an immediate voltage change across it. Any capacitor across the switch will experience infinite dV/dt and result in infinite current at the moment of transition (dt depends on simulation timestep now). However, in practice, we have inductance in series with any connection, which limits the rate of change of voltage. What you observe in SPICE generally more closely resembles the real-life situation. Please refer to this reference from Mike. Trap ringing is not an error, but telling you something can happen if you build such circuit.
Apparent Kirchhoff’s law violation - QSPICE - Qorvo Tech Forum
PLECS and PSIM are linear piecewise simulators for nonlinear devices. They are designed to handle discontinuities in the I-V curve, which are present in textbooks but not in real life. SPICE, on the other hand, focuses on real-life characteristics and addresses nonlinearity. That why you need some tweak in SPICE to work with near ideal model in general.
Here is my study of how trap ringing is present.
Stability of derivative function - QSPICE - Qorvo Tech Forum