Output of signed vector from Verilog

Hello, I was experimenting with the Verilog feature of QSPICE. Everything works great, but I’ve encountered something I can’t quite grasp.

I was attempting to simulate a 6-bit ADC (I know it’s a bit silly). The input is a sine wave, and the clock is used to sample it in accordance with the Shannon theorem. The ADC is represented as a Verilog instance with two input ports (clk and in) and two output ports (out1 and out2).

I used two output ports to illustrate my issue. out1 is a signed char (byte in Verilog), while out2 is a signed bit vector of 7 bits (1 bit more than 6 to accommodate the two’s complement sign, I added the signed keyword in Verilog).

After running the simulation, the plot viewer displays the following:

I’m having trouble understanding why the signed vector at the out2 output loses its sign and becomes unsigned.
However, when I examine the Main C++ code generated after compilation, I see that out2 is treated as an unsigned char by Verilator.

Is this a problem with Verilator (I found this on the web) or am I overlooking something obvious? Is there a way to obtain negative numbers as output from a Verilog vector?

Thank you for taking the time to read this and best regards.

PS - I’m unable to upload the schematic and the Verilog files, the site complains with me, sorry.

I’ve also attempted to use C++ to create the ADC in a new C++ template. However, right from the outset, the template appears to be incorrect.

But also when I correct it, like this:

The plot is the same as in Verilog.

So, my question is: is the Bit vector data type only applicable to Verilog templates? Additionally, is it exclusively unsigned? I’ve included images below to illustrate where I encountered this data type.

I believe everything is working as designed in verilog. It looks like the waveform viewer has no way to tell if the integer is a signed integer. The result is correct if you look at the binary representation of a signed number and how its going positive when it hits -1. Your next project should be to create a signed integer 6-bit DAC now.

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Thank you for your response. Yes, I understand now.

Initially, when using $display("%b\t%d\n", out2, out2), I observed that the representation is preserved. I had concerns that the representation of the numbers from the output (in this case, out2) wouldn’t be maintained outside of Verilog. This concern arose because the waveform viewer did not interpret them as negative, and the C++ DLL generated treated them as unsigned char.

Thanks to your suggestion, I added another Verilog block, and indeed, the representation is preserved (I also included the signed attribute for the input vector):


So, talking to myself: treat those numbers as you want, the next stage will decide if the sequence of bit will be signed or unsigned (I taught that the C++ compiler would make this automatically).

I learnt something new. WOW QSPICE.


Glad everything worked out. QSPICE is a fun tool with verilog and C++ access.

I believe that most processors use the same ADD instruction for signed and unsigned. It’s only needed for when we display the integer.

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