Dear,
For testing purposes I am trying to clock synchronize multiple anchors. I am using a single clock source and am now implementing One Shot Timebase Reset.
The OSTR I have implemented seems to work a little, but by far not with the specified accuracy of <300ps.
I have tested this by having the anchors transmit a message one by one with a fixed delay in between. The transmission times are based on the system clock and hence should be synchronized. When however receiving these message on a different unit, recording the reception time, and compensating for the transmission delays, I am still left with a significant timedifference of reception (I have seen as much as 3ms difference left).
On top of that, these timedifferences between anchors are different each time I do a OSTR. For example, the one time the difference between reception time of two anchors (after compensating for transmission delay) is 1ms (and is consistent until the next OSTR) and after an OSTR, the time difference is -2ms.
This significant time difference and the fact that after every OSTR these time differences are completely different, leads me to believe that I am doing something wrong with executing the OSTR (although it is executed somewhat OK as the difference is only some milliseconds).
What I do is:
dwt_forcetrxoff();
dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ESYNCR);
uint8_t waitCounter = 33; //see Application note APS007 p. 12
dwt_write32bitoffsetreg(EXT_SYNC_ID, EC_CTRL_OFFSET, EC_CTRL_OSTRM | EC_CTRL_PLLLCK | ((waitCounter << 3) & EC_CTRL_WAIT_MASK));
//volatile uint32_t dwtTime = dwt_readsystimestamphi32();
//wait for interrupt with status SYS_STATUS_ESYNCR
uint32 status = dwt_read32bitreg(SYS_STATUS_ID);
while ((status & SYS_STATUS_ESYNCR) == 0){
__WFI();
status = dwt_read32bitreg(SYS_STATUS_ID);
//dwtTime = dwt_readsystimestamphi32();
}
dwt_write32bitoffsetreg(EXT_SYNC_ID, EC_CTRL_OFFSET, 0);
dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ESYNCR);
dwt_forcetrxoff();
In application note APS007 it is stated that after an OSTR the offset between clocks of anchors is only caused by the propagation delay of the sync signal. I however have made sure that the wire over which the sync signal is transmitted is short and is equally long for each anchor. Still I am left with inconsistent results.
Could somebody please help me?
Kind regards,
Rick