Past - I have 2 DW1000s communicating okay
Current problem - I have started using a DW3120 and cannot get it to detect the preamble from my DW1000.
The DW1000 is setup as (ch 5):
DW1000.enableMode(DW1000.MODE_LONGDATA_FAST_ACCURACY);
The DW3120 after setup just sits in RX_STATE: PREAMBLE_FND
Any help pointing out my errors would be appreciated.
The output from the setup is as follows:
Reading Device ID:
DE CA 03 12
PDoA Version
DW3000 detected
Qorvo Device
Here begineth the SPI test
Writing to scratch RAM: AA
Contents of scratch RAM: AA
writing FD BC
FD BC
ANDing with 5D 08
5D 8
ORing with 22 24
7F 2C
Here endeth the SPI test
Clearing Pre-amble timout
Reading EVC_CTRL:
00 00 00 00
Enabling Pre-amble timout
Reading EVC_CTRL:
00 00 00 00
Setting up the RX TUNING registers for Channel 5 (User Man. Table 24)
Reading The RX Tuning (User Man. Table 24 for Channel 5)
DGC_CFG0 exp: 10 00 02 40 got: 10 00 02 40
DGC_CFG1 exp: 1B 6D A4 89 got: 1B 6D A4 89
DGC_LUT_0 exp: 00 01 C0 FD got: 00 01 C0 FD
DGC_LUT_1 exp: 00 01 C4 3E got: 00 01 C4 3E
DGC_LUT_2 exp: 00 01 C6 BE got: 00 01 C6 BE
DGC_LUT_3 exp: 00 01 C7 7E got: 00 01 C7 7E
DGC_LUT_4 exp: 00 01 CF 36 got: 00 01 CF 36
DGC_LUT_5 exp: 00 01 CF B5 got: 00 01 CF B5
DGC_LUT_6 exp: 00 01 CF F5 got: 00 01 CF F5
DGC_CFG E4 F5
Reading RF_CONF registers:
Exp ? RF_ENABLE 00 00 00 00
Exp ? RF_CTRL_MASK 00 00 00 00
Exp ? RX_CTRL_HI 08 B5 A8 33
Exp 1C 00 00 00 RF_SWITCH 1C 00 00 00
Exp 14 LDO_RLOAD 14
Exp 0E RF_TX_CTRL_1 0E
Exp 1C 07 11 34 RF_TX_CTRL_2 1C 07 11 34
Reading OTP Memory…
Addr 0x00 64 bit EUID 00 00 00 00
Addr 0x01 64 bit EUID 00 00 00 00
Addr 0x02 alt 64 bit EUID 00 00 00 00
Addr 0x03 alt 64 bit EUID 00 00 00 00
Addr 0x04 LDOTUNE_CAL 88 98 98 89
Addr 0x05 LDOTUNE_CAL 07 09 98 99
Addr 0x06 CHIP ID 58 AC 55 CD
Addr 0x07 LOT ID 02 12 02 58
Addr 0x08 VBAT 00 78 8F 40
Addr 0x09 Temp @ 22C 00 00 00 7E
Addr 0x0A BIASTUNE_CAL 00 11 00 13
Addr 0x0B Antenna Delay 7F BA 7F D5
Addr 0x0C AoA Iso 5D AC AD 88
Addr 0x0D W.S. Lot 00 00 00 00
Addr 0x0E W.S. Lot 00 00 00 00
Addr 0x0F W.S. Wafer 00 00 00 00
Addr 0x1E XTAL_TRIM 00 00 00 00
Addr 0x1F OTP Rev 00 00 00 00
Addr 0x20 DGC_CFG0 10 00 02 40
Addr 0x21 DGC_CFG1 1B 6D A4 89
Addr 0x22 DGC_CFG2 2D B6 C9 23
Addr 0x23 DGC_CFG3 12 20 6D B5
Addr 0x24 DGC_CFG4 24 91 B6 DA
Addr 0x25 DGC_CFG5 2D B6 49 24
Addr 0x26 DGC_CFG6 00 16 DB 6D
Addr 0x27 DGC_LUT_0 00 01 C0 FD
Addr 0x28 DGC_LUT_1 00 01 C4 3E
Addr 0x29 DGC_LUT_2 00 01 C6 BE
Addr 0x2A DGC_LUT_3 00 01 C7 7E
Addr 0x2B DGC_LUT_4 00 01 CF 36
Addr 0x2C DGC_LUT_5 00 01 CF B5
Addr 0x2D DGC_LUT_6 00 01 CF F5
Addr 0x35 PLL_CODE 00 00 1F 09
Addr 0x61 Q_RR 00 00 00 00
Setting up BIAS_CTRL
readback register BIAS_CTRL value: 10 11
Setting up FS_CTRL
Setting up PLL registers:
PLL Configuration should be Ch5: 1F 3C Ch9: 0F 3C
PLL Configuration: 1F 3C
If OTP PLL_LOCK_CODE has a non-zero value then use it in this register,
the USE_OLD bit should also be set
From reading OTP PLL_LOCK_CODE there is 00 00 1F 09
Default PLL Coarse Code should be 00 00 0F 0B
PLL Coarse Code: 00 00 0F 0B
Updating PLL Coarse Code should be 00 00 1F 09
PLL Coarse Code: 00 00 1F 09
PLL_CAL default is 0x31, optimal use 0x81 or 0x83 if USE_OLD
Readback PLL_CAL: 01 83
Setting up XTAL
readback register XTAL_Trim value: 00
if XTAL_Trim value == 0x00 then change to 0x2E:
readback register XTAL_Trim value: 2E
Reading Full ID:
00 00 00 00 00 00 00 00
Writing Full ID:
Reading Full ID:
84 00 5B D5 A9 9A E2 9C
Writing PANADR
Reading PANADR:
FF FF FF FF
Setting up SYS_CFG
System configuration register setting to 00 05 0D A8
Readback: 00 05 0D A8
Writing TX_CTRL
Reading TX_CTRL:
00 00 00 00 2C 0C
Reading CHAN_CTRL: 09 48
Reading OTP:
00 00 00 00
Reading 0x1C:
00 00 00 00
Reading The DRX Registers
DTUNE0 default is 1C 10
DTUNE0 10 1C
setting PAC size of 4 as recommended when receiving PAC size of 32…
Setting DTUNE0 to: 10 0F
DTUNE0 10 0F
RX_SFD_TOC should be numeric value
RX_SFD_TOC 00 41
PRE_TOC should be numeric value
PRE_TOC 00 00
PRE_TOC should be numeric value
PRE_TOC 00 00
DTUNE3 default is AF 5F 58 4C but needs to be AF 5F 35 CC
DTUNE3 AF 5F 58 4C
Setting up DTUNE_3
Now is: AF 5F 35 CC
DTUNE_5 is a reserved register
DTUNE_5 15 B4 B4 20
DRX_CAR_INT should be numeric value
DRX_CAR_INT 00 00 00
Calibrating Rx
Reading EC_CTRL: 00 00 10 04
Writing 0x00000004 to EC_CTRL:
Reading EC_CTRL: 00 00 00 04
Checking Cal Status: 00
Calibration not yet performed
Triggering Cal
Reading CAL_RX:
00 02 00 01
Checking Cal Status: 01
Calibration completed
Checking Calibration Result I: 10 88 82 10
Calibration Result I passed
Checking Calibration Result Q: 10 88 82 10
Calibration Result Q passed
Exiting Cal
Reading CAL_RX:
00 02 00 00