Hello everyone.
I’m starting to use Verilog. I had difficulty constructing a simple four-bit binary counter.
My output is a ladder, but I need binary digits. I found several examples in Verilog before looking into this issue and failed. Help me!
Here is my understanding based on a note in Ø-Device (.DLL).
You defined q as output, bit range [3]:[0], which is a digital 4-bit register in .DLL block. But whenever this signal return to schematic level it become analog voltages (discrete 0-15V). Therefore, if you need q[0], q[1], q[2] and q[3], you have to build a decode circuit in schematic level.
I am not 100% sure my understanding is correct, just share from my experience with Qspice so far.
Modify your method by taking advantage of bus in schematic to reduce size of symbol.
Parent.BusOutput.qsch (2.0 MB)
busoutput.v (505 Bytes)
Thank you very much. You helped me a lot.
