Logic gates problem?


I want to have at the output the square wave signals for a and b but having the positive amplitude Vdd and the negative amplitude Vss, independent the values at Vlogic_low and Vlogic_high. Also, it is not allowed to supply any of the 3 gates with Vlogic_high for Vdd and Vlogic_low for Vss. Is it possible such a thing?
Test2.qsch (8.2 KB)

Switching voltage for logic gates is (Vdd+Vss)/2 in this case switchig voltage is (50-20)/2 = 15 V, you can set reference voltage in attributes like REF=5 or change Vlogic high or low.

Best regards

Ivan1, I tried already this before posting. I think the problem is much more complicated than that. I was able to find particular cases where works, but right after I changed the value for Vlogic_high and Vlogic_low then the things mess up and start to not work anymore. But If You found a way You can post your solution.

The idea is this: I know that V2 will be a square wave signal having let’s say some unknown value for positive amplitude (Vlogic_high) and some unknown value for negative amplitude (Vlogic_low). Therefore whatever values will have Vlogic_high and Vlogic_low at V2, I need to be able to set the positive amplitude and negative amplitude for a and b square waves independent of values of Vlogic_high and Vlogic_low.

I thing that this problem does not have a solution, at least for the shown circuit. That’s why I posted this problem to see other people thinking.

if REF is assigned, the logic reference is at Vss+REF

This is the solution I can think of. Force the logic level to +1/-1 (I set input buffer with REF=1, where logic threshold is at 0V, you must determine where is logic input threshold). With logic at +1/-1V, you can scale your output with a B-source and if condition.

Just a remind, you are working on creating deadtime. If you have no plan to change deadtime during a .tran, better to use buffer with Td than B-source with delay.

Test2-KSKelvinR1.qsch (12.7 KB) : delay with B-source
Test2-KSKelvinR2.qsch (13.2 KB) : delay with buffer

Replace delay function with buffer Td

How to think about this REF associated with logic gates? Could you live more explanation about it? Its a threshold that does Something inside the gates? What does this REF attribute? And this REF attribute has effect only in the case of logic gates, right?

For instance parameter, you can always go to my device reference guide and search if I have that included and explanation can help or not.


Why the first schematic has such weird results? The results should look like in the second schematic.

Boost2.qsch (12.3 KB)
DeadTime.qsym (1.3 KB)

Boost1.qsch (16.4 KB)

It seems that:

But I do not know why this is happening

I think I can found: buffer needs also TTOL
DeadTime3.qsym (1.3 KB)

But there is still a difference:
With Boost2 schematic:

With Boost1 schematic:

With Boost2 schematic:

With Boost1 schematic:

did you upload your most update boost1 and boost2 .qsch?

Here I put both together for better visualization:

DeadTime3.qsym (1.3 KB)
Boost3.qsch (28.4 KB)

Symbol used:

do you still have a question or your problem already solved?

And if you want to have a look separately:

Boost 1 schematic:
Boost1.qsch (16.4 KB)

Boost 2 schematic:
DeadTime3.qsym (1.3 KB)
Boost2.qsch (12.4 KB)

The 2 schematic should have the same results…there is a slightly but noticeable difference…
Below is with R1 = R5 = 5R (constant value). This difference for sure matter…and is not good as this difference exist. They needs exactly match…


There is a difference between, from this comes I think


@KSKelvin From the above reason comes the difference and why the graphs not match exactly. Question: how to make LS_1 to match LS_2 (or the other way around, how to make both LS_2 to match LS_1). The same question for HS_1 and HS_2.


Do you know any explanation for this?

By putting that -10n and +10n:

DeadTime3.qsym (1.3 KB)
Boost3.qsch (28.0 KB)

I was able to match very closely (not yet exact match):