Large-Scale Power Electronics Simulation in QSPICE

Hi everyone,

I have two questions regarding large-scale power electronics simulation in QSPICE .

  1. Vectorization with DLL Blocks

I am planning to simulate multiple modular power converters with multiple input and output ports. My goal is to use vectorization to scale the schematic without modifying the existing circuit, similar to the vectorization approach used in PLECS.

Is such a workflow possible in QSPICE , particularly when using a DLL block ? Can a DLL process vector signals so that the same converter model can be replicated efficiently without manually creating hundreds of instances?

  1. Large-Scale Simulation of Converters

I am also interested in simulating large converter systems containing **hundreds of semiconductor switches (e.g., modular or multicell converter topologies).

–What are the major computational challenges when simulating such large-scale circuits in QSPICE?
– Are there recommended modeling techniques (e.g., behavioral models, averaging methods, vectorization, DLL-based approaches, hierarchical design, etc.) to improve simulation speed and scalability?
–Has anyone successfully simulated systems of this size in QSPICE? If so, I would appreciate any suggestions or best practices.

For reference, the type of vectorization I am referring to is described in the following resources:

https://onlinelibrary.wiley.com/doi/10.1002/9781119081371.ch3

Any insights, references, or examples would be greatly appreciated.

Thank you!

I think your aim is similar to what physicboy did. Please review it.

I am not able understand it.

DM me for more detail if needed…

Is vectorization in PLECS similar to buses and arrays in Qspice? It is basically a GUI-to-netlist feature.


@Mike2 This is not a large-scale simulation, but it basically demonstrates the use of a hierarchical block and a DLL controller to do things with buses and arrays. Well, currently, parameters in a hierarchical block cannot be passed to as a array (i.e. uses X[1:3] instead of X1, X2 and X3), and Mike is busy and may only be able to make a change a few weeks later. So, I didn’t demonstrate having the hierarchical block set up in an array. Once this is fixed, I will upload a new example.

From my experience, I seldom see very large-scale simulations in SPICE. Piecewise-linear (PWL) simulators like PSIM or PLECS may handle very complex systems, as their models are normally less complex than SPICE models, which limits complexity when scaling to many modules. And they have very strong library in simulating 3-phase and motors. I am not saying SPICE cannot do it, but simulators basically have their strengths and weaknesses. For example, I simulated a complex inverter with over 10 power amplifiers set up as hierarchical blocks, with each power amplifier using 4 FET (not ideal switch). But definitely I don’t have experience simulate something up to hundreds FETs.

example.Interleaved-Buck-Converter.qsch (6.6 KB)
buck-converter.qsch (13.9 KB)
controller.cpp (4.8 KB)

2 Likes

Bussed subcircuit version. Update Qspice to run this example.
07/29/2026 Improved ability to use parameters in bussed subcircuit instances.

example.Interleaved-Buck-Converter-Bussed.qsch (4.6 KB)

Supporting files

In case you are not using the DLL bit vector output (i.e., bussed output), here is an example of how to work with the bus. The gate signals are from g[1], g[2], and g[3], with net names in array format.

example.Interleaved-Buck-Converter-Bussed.qsch (7.6 KB)