Latch (Sample and Hold) is a ¥-Device. In the Qspice help, it doesn’t document the latch. However, if you go to Qspice Help and check ¥-Device, you will notice that all ¥-Device types are defined very similarly.
Logic has a reference level that determines HIGH/LOW, and it is set by REF. By default, it is half of Vdd and Vss. For example, if Vss=0 and Vdd=20, the threshold is 10V with respect to Vss. This applies to all logic inputs, such as both EN and CLK of the latch.
I have this study note for REF.
