I’m trying to communicate with an EEPROM (AT24 compatible, address: 0x50) using PAC5527. When trying a write operation (or read, doesn’t matter), I do the following:
// START
I2C.CONSET.STA = 1
Wait until I2C.STAT == 0x08
I2C.CONCLR.SIC = 1
// SLA+W
I2C.DAT = 0xA0 (0x50 << 1 | 0)
Wait until I2C.STAT == 0x18 (ACK) or 0x20 (NACK)
…
PCLK = 150MHz, M=5, N=4, fSCL~=93.75KHz
Apparently the 7th bit in the DAT register is ignored, as you can see in the captures:
So I think I have discovered the issue after observing that it is only present in debug builds (so much slower, not optimized).
Apparently, after sending the start bit, you need to write the address to the DAT register pretty fast; otherwise it seems to miss the 7th bit. If I write the data before sending the START, it seems to work fine regardless of optimization level, see:
The issue can easily be reproduced in optimized builds by inserting a small delay after clearing the interrupt, and before writing the address. I guess this should be documented somewhere?