Hysteresis on logic gates

Hello Community,
I recently had to use some logic gates IC to implement a functionality and in their datasheet they specify the upper and lower threshold in the model. Currently I use the trigger schmitt in the following configuration for the buffer.
It works fine, but the problem will be when I would have to scale with with analog circuits like some delays to obtain the desired result, the schematic may quite large to include also a schmitt trigger for every gate. Wouldnt that be easier to include the vt and vh to the logic gates?
Or it is this functionality, and I’ve missed it?

The gates and flops were for modeling ASICs, so no hysteresis isn’t included just like it isn’t included in real gates and flops.

You can make the Schmitts look a little more tidy, though. Specify a net name of “¥” for EN in the Symbol Properties Pane and that pin and functionally is gone. It will simply always be enabled.