How to generate delay times between two signals?


Is it possible to generate these two signals having 2 switches and 1 pulse signal that is driving the 2 switches? The problem is in how to make td1 and td2 (for example td1 = 10ns, td2 = 10ns)…
PULSE(0 10 0 1n 1n 1m 2m)
.model MYSW SW(Ron=0.1m Roff=100Meg Vt=0.005)

You want to create a symmetrical signal between S1 and S2, or S1 duty must be 50% (or certain value) and S2 is conjugate but with different deadtime td1 and td2?

Here is for symmetrical signal

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I know that this thing can be done with two signal pulses. The question was how to do this with 1 signal pulse only.

Not the only way to do it (but probably the most fun way) you can put in a delay filter and comparator.

or you can do it the SPICE voltage source way:

Also you can now use C++ and verilog, but someone else will need to demonstrate that.

Only a single source S1 in your system?
Imagine that, when S1 turn off, with a delay for S2 to turn on is easy. But how S2 know when to turn OFF if you only have one source in your system. You must have some sort of clk signal to help.

I found the way how to do this:
@KSKelvin can you translate this schematic in QSPICE?

This is how this circuit can be implemented in Qspice. Basically, this is symmetical and the trick is replicate master signal itself with an inverter (or in your example, B-source -V(a)+10)

I don’t like the idea of using -V(a)+10 as this is not something you will practically implement.
Therefore, I just simply use an inverter and change a bit of this logic implementation. Practical delay implementation is already mentioned by @jay314159265.

Deadtime for Symmetical Signal - Master Source Only.qsch (7.0 KB)

And how to change the amplitude of V(gate1) and V(gate2) to be 10V for high and 0V for low? right now is 1V for high and 0V for low

Here you go.

Deadtime for Symmetical Signal - Master Source Only - Vdd.qsch (7.1 KB)

This is practical circuit implementation with R-C delay.
Deadtime for Symmetical Signal - Master Source Only - Practical Delay.qsch (8.1 KB)

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For V(gate1) or V(gate2) from 1V peak to 10V peak, another way is just to use a B-source, with formula likes V=10*V(gate1).

I have done this for LTspice. Please, check out this video.
It can be done in the same way for Qspice.

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You can also use the idt() function to create a time to voltage converter with either behavioral voltage or current sources as is done in the LTspiceControlLibrary for their ComplementaryBufferWithDeadtime. Works well.

GitHub - kanedahiroshi/LTspiceControlLibrary: A LTspice library for designing controller by drwaing control block diagram

Here is a breakdown

ComplementaryBufferwithDeadtime.qsch (15.0 KB)

The programmable deadtime driver from @marcos.uniovi in previous reply is replicated in Qspice. This is the embedded symbol and demo schematic. Deadtime is controlled by an attribute tau.
+ProgDeadtime.qsym (1.6 KB)
Parent.+ProgDeadtime.qsch (4.9 KB)

Below is a full schematic of this driver as according Prof. Marcos youtube video. I made slightly modification by including a buffer at input signal to ensure voltage in next stage (with RC delay elements) must be 1V/0V to prevent input signal amplitude affect deadtime calculation. In addition, the logic threshold of ¥1 and ¥2 are set to e^-1 or 1-e^-1, which is also to ensure deadtime match RC time constant. Hope that I don’t make any mistake in this LTspice replication work.
Programmable Deadtime Driver.qsch (27.3 KB)


This is great. Thank you very much for this effort.