I tried to add a delay statement to a Verilog code block but it seems that the # synthax is not recognized.
It seems that in the most recent versions, Verilator supports delay statements.
To do so the argument “–timing” should be added to the Verilator command line argument.
Can this be done in Qspice?
Is there a way to implement a delay directly in C++?
I’ve never gotten Verilator to support timing. In fact, Verilog is usually presented as being capable of synthesizable Verilog, meaning no timing, even though behavior Verilog constructs are supported.
But the Verilator is one rev back from current, so I’ll be updating it and see if it can do timing. I’m hoping $monitor works now. It’s documented in the Verilator documentation, but from looking at the Verilator source code, it seems to be only partially implemented. It seems that some Verilator features are only supported if used in conjunction with SystemC. I’m bypassing SystemC and going straight to the metal in QSPICE.
–Mike
Thanks Mike. For the time being I have implemented it in C++ and it works greatly. New questions arose, but will post them separately.
