Higher Vds_on when SiC current is reversed

I have created the schematic below to compare the voltage drop across a built-in SiC mosfet in QSPICE. The result shows that the voltage drop at net M2 is higher than the voltage drop at net M1 in the on condition. Aren’t they supposed to have the same voltage drop in the “on” condition?

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There would be a slight difference, due to different voltages drop across source vs drain resistances when inverted because the different drop across the source(or drain used as source) gobbling up a different amount of the extrinsic gate-source voltage, but nowhere never that large.

There was a problem in the Level 2010 MOSFET device equations. It’s fixed now. Please do an update.


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Thanks. Confirmed, it is fixed now. - Andrew