Hi, all
When simulation half-bridge with Infineon’s GaN model, the simulation stopped with timestep too small.
I’ve tried reduce the accuracy but didn’t help much. Hope to get help!
CoolGaN_Transistor_650V_G5_Spice.txt (64.2 KB)
HB_GaN.qsch (8.4 KB)
– Peter
Thanks. Tried .options trtol=1, but the simulation was very slow at about 1us and the timestep reduced to about 2.5ps.
–Peter
If someone can run a simulation quickly but you are unable to do so, switch the simulator from Qspice64.exe to Qspice80.exe as a test. Some users have fastmath disabled by default in Preferences. These two options can help convergence in this schematic.
.option trtol=.1 fastmath=0
OR, as @EL34 suggestion, change to gear with trtol reduces to 1.
.option method=gear trtol=1 fastmath=0
If almost a MUST to use Qspice80.exe for Infineon’s model, as they are essentially a collection of mathematic formula implementation and requires higher precision math to process.
Hi, Kelvin
With these options, the simulation converges. Thanks a lot!
And can increase RELTOL to balance speed and precision.
.options fastmath=0
.options TRTOL=0.1 RELTOL=0.005
– Peter
Hi Peter,
Timestep too small means that the solver does not converge, even after reducing the timesteps to very small numbers.
In your simulation, the simulator aggressively increases the timestep between switching events to 100ns between points. It can’t reduce the timestep fast enough when solving a switching event, where you would want sub-nanosecond resolution.
Start by setting the maximum timestep to 1ns in your simulation command and only keep the gear integration option
.tran 0 .1m 0 1n
.option method=gear
The simulator will have an easier time at the beginning of a switching event and should give you a lot less timestep errors. Of course, there is a downside, the simulator will now waste a lot of time between switching events and your simulations will take a long time to execute.
If you modify your circuit to make the switching less eventful (limit current with small resistors everywhere, limit the frequency content with small inductors and capacitors everywhere, avoid shoot-through), then you should be able to increase the minimum timestep to something more tolerable like 5ns or 10ns.
Here is a screenshot of a switching event after lowering the gate resistors to 2.2ohms (Infineon tested the rise/fall times of the IGT65R025D2 with that value). You can see that the fast dv/dt of the SW node is pulling DRVL up to dangerous levels for a GaN. Those transistors will be happier with a split-drive and a very strong ROFF. Soft-switching would be even better.
