What is the best topology to use for a negative voltage generator to supply the gate bias of a GaN power transistor. To initially provide the negative voltage bias but also someway to adjust Idsq.
Hello. I will attach and older app note that helps to explain the basics with discrete circuit ideas. We also have our ACT43750
Bias Techniques for GaN and PHEMT Depletion Mode Devices - 09-16-14.pdf (1.2 MB)
GaN bias IC.